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CY2313ANZ Dataheets PDF



Part Number CY2313ANZ
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Datasheet CY2313ANZ DatasheetCY2313ANZ Datasheet (PDF)

www.DataSheet4U.com 0NZCY2310 13ANZ CY2313ANZ 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Features • One input to 13 output buffer/driver • Supports up to three SDRAM DIMMs • One additional outputs for feedback • Serial interface for output control • Low skew outputs • Up to 100-MHz operation • Multiple VDD and VSS pins for noise reduction • Low EMI outputs • 28-pin SOIC (300-mil) package • 3.3V operation Functional Description The CY2313ANZ is a 3.3V buffer designed to distribu.

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www.DataSheet4U.com 0NZCY2310 13ANZ CY2313ANZ 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Features • One input to 13 output buffer/driver • Supports up to three SDRAM DIMMs • One additional outputs for feedback • Serial interface for output control • Low skew outputs • Up to 100-MHz operation • Multiple VDD and VSS pins for noise reduction • Low EMI outputs • 28-pin SOIC (300-mil) package • 3.3V operation Functional Description The CY2313ANZ is a 3.3V buffer designed to distribute high-speed clocks in desktop PC applications. The part has 13 outputs, 12 of which can be used to drive up to three SDRAM DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 100 MHz, thus making it compatible with Pentium® II processors. The CY2313ANZ can be used in conjunction with the CY2280, CY2281, CY2282 or similar clock synthesizer for a complete Pentium II motherboard solution. The CY2313ANZ also includes a serial interface which can enable or disable each output clock. On power-up, all output clocks are enabled. Block Diagram Pin Configuration BUF_IN SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN SDRAM4 SDRAM5 SDRAM12 VDDIIC SDATA 28 SOIC Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SDATA Serial Interface Decoding SCLOCK VDD SDRAM11 SDRAM10 VSS VDD SDRAM9 SDRAM8 VSS VDD SDRAM7 SDRAM6 VSS VSSIIC SCLK Pentium is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-07144 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 DataSheet 4 U .com www.DataSheet4U.com CY2313ANZ Pin Summary Name VDD VSS VDDIIC VSSIIC BUF_IN SDATA SCLK SDRAM [0-12] Pins 1, 5, 20, 24, 28 4, 8, 17, 21, 25 13 16 9 14 15 2, 3, 6, 7, 10, 11, 12, 18, 19, 22, 23, 26, 27 Description 3.3V Digital voltage supply Ground Serial interface voltage supply Ground for serial interface Input clock Serial data input, internal pull-up to VDD Serial clock input, internal pull-up to VDD SDRAM clock outputs Serial Configuration Map • The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 • Reserved and unused bits should be programmed to “0” • Serial interface address for the CY2313ANZ is: A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ---- Byte 1: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 27 26 23 22 --19 18 Description SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) Reserved, drive to 0 Reserved, drive to 0 SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) Byte 0:SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enabled Bit Pin # Description SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Reserved, drive to 0 Reserved, drive to 0 SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Bit 7 11 Bit 6 10 Bit 5 -Bit 4 -Bit 3 7 Bit 2 6 Bit 1 3 Bit 0 2 Byte 2: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -12 ------Pin # Description Reserved, drive to 0 SDRAM12 (Active/Inactive) Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 Document #: 38-07144 Rev. *A Page 2 of 8 DataSheet 4 U .com www.DataSheet4U.com CY2313ANZ Maximum Ratings Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage (Except BUF_IN)........ –0.5V to VDD + 0.5V DC Input Voltage (BUF_IN)............................ –0.5V to +7.0V Storage Temperature ................................. –65°C to +150°C Junction Temperature................................................. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions[1] Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 Description Min. 3.135 0 Max. 3.465 70 30 7 50 Unit V °C pF pF ms Electrical Characteristics Over the Operating Range Parameter VIL VILiic VIH IIL IIL IIH VOL VOH IDD IDD IDD IDD IDDS Description Input LOW Voltage[2] Input LOW Voltage Input HIGH Voltage[2] Input LOW Current (BUF_IN input) Input LOW Current (Except BUF_IN Pin) Input HIGH Current Output LOW Voltage[3] Output HIGH Supply Supply Voltage[3] Current[3] Current[3] VIN = 0V VIN = 0V VIN = VDD IOL = 25 mA IOH = –36 mA Unloaded outputs, 100 MHz Loaded outputs, 100 MHz Unloaded outputs, 66.67 MHz Loaded outputs,.


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