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Integrated Circuit Systems, Inc.
ICS954201
Programmable Timing Control Hub™ for Mobile P4™ Systems
Recommended Application: CK410M clock, Intel Yellow Cover part Output Features: • 2 - 0.7V current-mode differential CPU pairs • 7 - 0.7V current-mode differential SRC pair for SATA and PCI-E • 1 - 0.7V current-mode differential CPU/SRC selectable pair • 4 - PCI (33MHz) • 2 - PCICLK_F, (33MHz) free-running • 1 - USB, 48MHz • 1 - DOT, 96MHz, 0.7V current differential pair • 1 - REF, 14.318MHz Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC outputs cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 500ps • +/- 300ppm frequency accuracy on CPU & SRC clocks • +/- 100ppm frequency accuracy on USB clocks Pin Configuration
VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0 PCICLK_F1 Vtt_PwrGd#/PD VDD48 USB_48MHz/FS_A GND DOTT_96MHz DOTC_96MHz FS_B/TEST_MODE SRCCLKT0 SRCCLKC0 SRCCLKT1 SRCCLKC1 VDDSRC SRCCLKT2 SRCCLKC2 SRCCLKT3 SRCCLKC3 SRCCLKT4_SATA SRCCLKC4_SATA VDDSRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCICLK2 PCI/SRC_STOP# CPU_STOP# FS_C/TEST_SEL REFOUT GND X1 X2 VDDREF SDATA 1. SCLK GND 2. CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 IREF GNDA VDDA CPUCLKT2_ITP/SRCCLKT7 CPUCLKC2_ITP/SRCCLKC7 VDDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 GND
Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA and PCI-Express • Supports spread spectrum modulation, 0 to -0.5% down spread • • • Supports CPU clocks up to 400MHz Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Supports undriven differential CPU, SRC pair in PD# for power management.
Functionality
FS_C 0 0 0 0 1 1 1 1
1
FS_B FS_A 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
2
2
CPU SRC MHz MHz 266.66 100.00 133.33 100.00 200.00 100.00 166.66 100.00 333.33 100.00 100.00 100.00 400.00 100.00 RESERVED
PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33
REF MHz 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
USB MHz 48.00 48.00 48.00 48.00 48.00 48.00 48.00 48.00
DOT MHz 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00
FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values.
56-pin SSOP & TSSOP
0819G—12/06/04
ICS954201
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ICS954201
Pin Description
PIN # PIN NAME 1 2 3 4 5 6 7 8 9 VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0 PCICLK_F1 PIN TYPE PWR PWR OUT OUT OUT PWR PWR I/O OUT DESCRIPTION Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP#. ITP_EN: latched input to select pin functionality 1 = CPU_ITP pair 0 = SRC pair Free running PCI clock not affected by PCI_STOP# . Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. Power pin for the 48MHz output.3.3V Frequency select latch input pin / Fixed 48MHz USB clock output. 3.3V. Ground pin. True clock of differential pair for 96.00MHz DOT clock. Complement clock of differential pair for 96.00MHz DOT clock. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC/SATA pair. Complement clock of differential SRC/SATA pair. Supply for SRC clocks, 3.3V nominal
10
Vtt_PwrGd#/PD
IN
11 12 13 14 15
VDD48 USB_48MHz/FS_A GND DOTT_96MHz DOTC_96MHz
PWR I/O PWR OUT OUT
16
FS_B/TEST_MODE
IN
17 18 19 20 21 22 23 24 25 26 27 28
SRCCLKT0 SRCCLKC0 SRCCLKT1 SRCCLKC1 VDDSRC SRCCLKT2 SRCCLKC2 SRCCLKT3 SRCCLKC3 SRCCLKT4_SATA SRCCLKC4_SATA VDDSRC
OUT OUT OUT OUT PWR OUT OUT OUT OUT OUT OUT PWR
0819G—12/06/04
2
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ICS954201
Pin Description (Continued)
PIN # 29 30 31 32 33.