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PRELIMINARY
CY7C1511V18 CY7C1526V18 CY7C1513V18 CY7C1515V18
72-Mbit QDR™-II SRAM 4-Word Burst Architecture
Features
Separate Independent Read and Write Data Ports — Supports concurrent transactions 250-MHz Clock for High Bandwidth 4-Word Burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both Read and...
