Mobile Low-Power DDR SDRAM
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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile DDR SDRAM
Mobile Double Data Rate (DDR) SDRAM
MT46H...
Description
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Preview‡
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile DDR SDRAM
Mobile Double Data Rate (DDR) SDRAM
MT46H16M16LF – 4 Meg x 16 x 4 Banks MT46H8M32LF – 2 Meg x 32 x 4 Banks
For a complete data sheet, please refer to www.micron.com/mobileds.
Features
VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V Bidirectional data strobe per byte of data (DQS) Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Differential clock inputs (CK and CK#) Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs Four internal banks for concurrent operation Data masks (DM) for masking write data–one mask per byte Programmable burst lengths: 2, 4, 8, 16 or full page Concurrent auto precharge option is supported Auto refresh and self refresh modes 1.8V LVCMOS compatible inputs On-chip temperature sensor to control refresh rate Partial array self refresh (PASR) Deep power-down (DPD) Selectable output drive (DS) Clock stop capability
Figure 1: 60-Ball VFBGA Assignment
1 A
VSS DQ15 VSSQ VDDQ DQ0 VDD
2
3
4
5
6
7
8
9
B
VDDQ DQ13 DQ14 DQ1 DQ2 VSSQ
C
VSSQ DQ11 DQ12 DQ3 DQ4 VDDQ
D
VDDQ DQ9 DQ10 DQ5 DQ6 VSSQ
E
VSSQ UDQS DQ8 DQ7 LDQS VDDQ
F
VSS UDM NC A13, NC LDM VDD
G
CKE CK CK# WE# CAS# RAS#
H
A9 A11 A12 CS# BA0 BA1
J
A6 A7 A8 A10/AP A0 A1
K
VSS A4 A5 A2 A3 VDD
Options
VDD/VDDQ 1.8V/1.8V Configuration 16 Meg x 16 (4 Meg x 16 x 4 banks) 8 Meg x 32 ...
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