(CY7C09xx9V) 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
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25/0251
CY7C09079V/89V/99V CY7C09179V/89V/99V
3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static...
Description
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25/0251
CY7C09079V/89V/99V CY7C09179V/89V/99V
3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
Features
True Dual-Ported memory cells which allow simultaneous access of the same memory location 6 Flow-Through/Pipelined devices — 32K x 8/9 organizations (CY7C09079V/179V) — 64K x 8/9 organizations (CY7C09089V/189V) — 128K x 8/9 organizations (CY7C09099V/199V) 3 Modes — Flow-Through — Pipelined — Burst Pipelined output mode on both ports allows fast 100-MHz operation 0.35-micron CMOS for optimum speed/power
v
High-speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.) 3.3V low operating power — Active= 115 mA (typical) — Standby= 10 µA (typical) Fully synchronous interface for easier operation Burst counters increment addresses internally — Shorten cycle times — Minimize bus noise — Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP
Logic Block Diagram
R/WL OEL R/WR OER
CE0L CE1L
1
0/1
1
0/1
0
0
CE0R CE1R
FT/PipeL
[2]
0/1
1
0
0
1
0/1
FT/PipeR
[2]
8/9
8/9
I/O0L–I/O7/8L I/O Control
[3]
I/O0R–I/O7/8R I/O Control
15/16/17
[3]
15/16/17
A0–A14/15/16L CLKL ADSL CNTENL CNTRSTL
Counter/ Address Register Decode
True Dual-Ported RAM Array
Counter/ Address Register Decode
A0–A14/15/16R CLKR ADSR CNTENR CNTRSTR
Notes: 1. See page 6 for Load Conditions. 2. I/O0–I/O7 for x8 devices, ...
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