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25/0251
CY7C09089/99 CY7C09189/99
64K/128K x 8/9 Synchronous Dual-Port Static RAM
Features
• True dual-ported memory cells which allow simultaneous access of the same memory location • Six Flow-Through/Pipelined devices — 64K x 8/9 organizations (CY7C09089/189) — 128K x 8/9 organizations (CY7C09099/199) • Three Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 100MHz cycle time • 0.35-micron CMOS for optimum speed/power • High-speed clock to data access 6.5[1]/7.5/9/12 ns (max.) • Low operating power — Active = 195 mA (typical) — Standby = 0.05 mA (typical) • Fully synchronous interface for easier operation • Burst counters increment addresses internally — Shorten cycle times — Minimize bus noise • • • • • — Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP Pin-compatible and functionally equivalent to IDT70908 and IDT709089
Logic Block Diagram
R/WL OEL R/WR OER
CE0L CE1L
1
0/1
1
0/1
0
0
CE0R CE1R
FT/PipeL
[2]
0/1
1
0
0
1
0/1
FT/PipeR
[2]
8/9
8/9
I/O0L–I/O7/8L I/O Control
[3]
I/O0R–I/O7/8R I/O Control
16/17
[3]
16/17
A0–A15/16L CLKL ADSL CNTENL CNTRSTL
Counter/ Address Register Decode
True Dual-Ported RAM Array
Counter/ Address Register Decode
A0–A15/16R CLKR ADSR CNTENR CNTRSTR
Notes: 1. See page 7 for Load Conditions. 2. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices. 3. A0–A15 for 64K; and A0–A16 for 128K devices.
For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-06039 Rev. *A Revised December 27, 2002
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Functional Description
The CY7C09089/99 and CY7C09189/99 are high-speed synchronous CMOS 64K and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[4] Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 15 ns after the address is clocked into the device. Pipelined output or flowthrough mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOWto-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe (ADS). When the port’s Count Enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.
Note: 4. When writing simultaneously to the same location, the final value cannot be guaranteed.
Document #: 38-06039 Rev. *A
Page 2 of 19
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Pin Configurations
100-Pin TQFP (Top View)
CNTENR CNTENL ADSR CLKR ADSL CLKL GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A6L
A5L
A4L
A3L
A2L
A1L
A0L
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L [5] A16L VCC NC NC NC NC CE0L CE1L CNTRSTL R/WL OEL [6] FT/PIPEL NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R A16R GND NC NC NC NC CE0R CE1R CNTRSTR R/WR OER FT/PIPER GND NC [6] [5]
CY7C09099 (128K x 8) CY7C09089 (64K x 8)
NC 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC
I/01R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O0R
I/O7R
GND
VCC
GND
VCC
NC
GND
NC
I/O2L
I/O1L
I/O7L
I/O6L
I/O5L
I/O4L
Notes: 5. This .