T14L1024A

www.DataSheet4U.com tm TE CH Preliminary T14L1024A SRAM FEATURES Fast Address Access Times : 10/12/15ns Single 3.3V ±0.3V power supply Low Power Consumption : 110/105/100mA TTL I/O compatible 2.0V data retention mode Automatic power-down when deselected Available packages : 32-pin 300 mil DIP/SOJ & 32-pin SOP/TSOP-I Industry Standard Pin Assignment 128K X 8 HIGH SPEED CMOS STATIC RAM GENERAL DESCRIPTION The T14L1024A is a one-megabit density, fast static random access memory organized as 131,072 words by 8 bits. It is designed for use in high performance memory applications such as main memory storage and high speed communication buffers. Fabricated using high performance CMOS technology, access times down to 10ns are achieved. Memory expansion by banking is easily accomplished using the chip enable pins CE1 and CE2. This device is packaged in a standard 32-pin 300 mil DIP/SOJ and 32-pin SOP/TSOP-I. BLOCK DIAGRAM Vcc Vss A0 . . . . A16 CE1 CE2 DATA I/O WE OE CORE ARRAY PIN CONFIGURATION NC A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 Vcc A11 CE2 WE A12 A13 A14 A15 OE A16 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 DECODER DIP / SOJ / SOP 28 27 26 25 24 23 22 21 20 19 18 17 I/O0 . . . I/O7 PIN DESCRIPTION SYMBOL A0 - A16 I/O0 - I/O7 /CE1,CE2 /WE /OE Vcc Vss DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Output Enable Power Supply Ground A15 A14 A13 A12 WE CE2 A11 VCC NC A1...