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ATF1508SE Dataheets PDF



Part Number ATF1508SE
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description EEPROM
Datasheet ATF1508SE DatasheetATF1508SE Datasheet (PDF)

www.DataSheet4U.com Features • 2nd Generation EE PROM-based Complex Programmable Logic Devices – VCCIO of 5.0V or 3.3V with 3.3V Operation being 5V Tolerant – 32 - 256 Macrocells with Enhanced Features – Pin-compatible with Industry Standard Devices – Speeds to 5 ns Maximum Pin-to-pin Delay – Registered Operation to 250 MHz Enhanced Macrocells with Logic Doubling™ Features – Bury Either Register or COM while Using the Other for Output – Dual Independent Feedback Allows Multiple Latch Functions .

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www.DataSheet4U.com Features • 2nd Generation EE PROM-based Complex Programmable Logic Devices – VCCIO of 5.0V or 3.3V with 3.3V Operation being 5V Tolerant – 32 - 256 Macrocells with Enhanced Features – Pin-compatible with Industry Standard Devices – Speeds to 5 ns Maximum Pin-to-pin Delay – Registered Operation to 250 MHz Enhanced Macrocells with Logic Doubling™ Features – Bury Either Register or COM while Using the Other for Output – Dual Independent Feedback Allows Multiple Latch Functions per Macrocell – 5 Product Terms per Macrocell, expandable to 40 per Macrocell with Cascade Logic, Plus 15 more with Foldback Logic – D/T/Latch Configurable Flip-flops plus Transparent Latches – Global and/or per Macrocell Register Control Signals – Global and/or per Macrocell Output Enable – Programmable Output Slew Rate per Macrocell – Programmable Output Open Collector Option per Macrocell – Fast Registered Input from Product Term Enhanced Connectivity – Single Level Switch Matrix for Maximum Routing Options – Up to 40 Inputs per Logic Block Advanced Power Management Features – ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and I/O for µA Level Standby Current for “L” Versions – Pin-controlled 1 mA Standby Mode – Reduced-power Option per Macrocell – Automatic Power Down of Unused Macrocells – Programmable Pin-keeper Inputs and I/Os Available in Commercial and Industrial Temperature Ranges Available in All Popular Packages Including PLCC, PQFP and TQFP EE PROM Technology – 100% Tested – Completely Reprogrammable – 10,000 Program/Erase Cycles – 20 Year Data Retention – 2000V ESD Protection – 200 mA Latch-up Immunity JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993 – Pull-up Option on JTAG Pins TMS and TDI IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG PCI-compliant Security Fuse Feature • ATF15xxSE Family Datasheet ATF1502SE(L) ATF1504SE(L) ATF1508SE(L) ATF1516SE(L) Preliminary • • • • • • • • • Rev. 2401D–PLD–09/02 1 DataSheet 4 U .com www.DataSheet4U.com General Description Beginning with the introduction of the 100% connected ATF1500 with 32 enhanced macrocells in 1996, Atmel’s CPLD products have delivered extra IO connectivity and logic reusability. Atmel’s commitment to efficient, flexible architecture has continued with the current Atmel ATF15xxSE Family of industry-standard, pin-compatible CPLDs. Atmel’s Logic Doubling architecture consists of wider fan-in, additional routing and clock options, combined with sophisticated, proprietary device fitters, extend CPLD place and route efficiency. Atmel enhanced macrocell includes double independent buried feedback that allows designers to pack more logic (particularly shifters and latches) into a smaller CPLD or leave spare room for later revisions. The Atmel ATF15xxSE family delivers enhanced functionality and flexibility with no additional design effort and is highly cost effective. The Atmel ATF15xxSE Family includes all popular configurations and speeds. Table 1. ATF15xxSE Family Device Features Feature Usable Gates Macrocells Logic Blocks Max. # Pins Max. User I/Os TPD Grades (ns) ATF1502SE(L) 750 32 2 44 36 5, 6, 7, 10(15) ATF1504SE(L) 1500 64 4 100 68 5, 6, 7, 10(15) ATF1508SE(L) 3000 128 8 256 100 6, 7, 10(15) ATF1516SE(L) 6000 256 16 256 164 7, 10(15) The Atmel ATF15xxSE Family includes pin-compatible products in all popular packages. Table 2. ATF15xxSE Family Device Packages and Number of Signal Pins(1)(2) Packages 44-pin PLCC 44-pin TQFP 84-pin PLCC 100-pin TQFP 100-pin PQFP 160-pin PQFP 208-pin PQFP 208-pin RQFP Notes: ATF1502SE(L) 36 36 ATF1504SE(L) 36 36 68 68 68 84 84 100 164 164 ATF1508SE(L) ATF1516SE(L) 1. Contact Atmel for up-to-date information on device and package availability. 2. When the JTAG port is used for In System Programming (ISP) or Boundary-scan Testing (BST), the four associated pins become JTAG pins and are unavailable for user I/O. 2 ATF15xxSE Family 2401D–PLD–09/02 DataSheet 4 U .com www.DataSheet4U.com ATF15xxSE Family Functional Description The ATF15xxSE Family of 5.0 Volt supply, high-performance, high-density complex programmable logic devices (CPLDs) utilizes Atmel’s proven electrically erasable non-volatile technology. With up to 512 macrocells, they easily integrate logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF15xxSE Family’s enhanced macrocell architecture, switch matrices and routing increase usable gate count for new designs and increase odds of successful pin-locked design modifications while maintaining pin-compatibility with industry standard CPLDs. The ATF15xxSE Family devices have four dedicated input pins and depending on the type of device and package, up to 208 bi-directional I/O pins. Each dedicated input pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Each input.


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