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CY7C1223F
2-Mb (128K x 18) Pipelined DCD Sync SRAM
Features
Registered inputs and outputs for pipelined operation Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state 128K × 18-bit common I/O architecture 3.3V –5% and +10% core power supply (VDD) 3.3V I/O supply (VDDQ) Fast clock-to-output tim...
