M50FLW040A

www.DataSheet4U.com M50FLW040A M50FLW040B 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory PRELIMINARY DATA FEATURES SUMMARY s s s s s s s FLASH MEMORY – Compatible with either the LPC interface or the FWH interface (Intel Spec rev1.1) used in PC BIOS applications – 5 Signal Communication Interface supporting Read and Write Operations – 5 Additional General Purpose Inputs for platform design flexibility – Synchronized with 33MHz PCI clock 8 BLOCKS OF 64 KBYTES – 5 blocks of 64 KBytes each – 3 blocks, subdivided into 16 uniform sectors of 4 KBytes each Two blocks at the top and one at the bottom (M50FLW040A) One block at the top and two at the bottom (M50FLW040B) ENHANCED SECURITY – Hardware Write Protect Pins for Block Protection – Register-based Read and Write Protection SUPPLY VOLTAGE – VCC = 3 to 3.6V for Program, Erase and Read Operations – VPP = 12V for Fast Program and Erase TWO INTERFACES – Auto Detection of Firmware Hub (FWH) or Low Pin Count (LPC) Memory Cycles for Embedded Operation with PC Chipsets – Address/Address Multiplexed (A/A Mux) Interface for programming equipment compatibility. PROGRAMMING TIME: 10µs typical PROGRAM/ERASE CONTROLLER – Embedded Program and Erase algorithms – Status Register Bits Figure 1. Packages PLCC32 (K) TSOP32 (NB) 8 x 14mm TSOP40 (N) 10 x 20mm s s PROGRAM/ERASE SUSPEND – Read other Blocks/Sectors during Program Suspend – Program other Blocks/Sectors during Erase ...