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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21356-3E
ASSP
Dual Serial Input PLL Frequency Synthesizer
MB15F02SL
s DESCRIPTION
The Fujitsu MB15F02SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1200 MHz and a 500 MHz prescalers. The 1200 MHz and 500 MHz prescalers have a dual modulus division ratio of 128/129 or 64/65, and a 8/9 or a 16/17 enabling pulse swallowing operation. The supply voltage range is between 2.4 V and 3.6 V. The MB15F02SL uses the latest BiCMOS process. As a result, the supply current is typically 3 mA at 2.7 V. A refined charge pump supplies a well-balanced output current of 1.5 mA or 6 mA. The charge pump current is selectable by serial data. MB15F02SL is ideally suited for wireless mobile communications, such as GSM and PDC.
s FEATURES
• High frequency operation: RF synthesizer: 1200 MHz max IF synthesizer: 500 MHz max • Low power supply voltage: VCC = 2.4 to 3.6 V • Ultra Low power supply current: ICC = 3.0 mA typ. (VCC = 2.7 V, Ta = +25°C, in IF, RF locking state) ICC = 3.5 mA typ. (VCC = 3.0 V, Ta = +25°C, in IF, RF locking state) • Direct power saving function: Power supply current in power saving mode Typ. 0.1 µA (VCC = 3.0 V, Ta = +25°C), Max. 10 µA (VCC = 3.0 V) • Dual modulus prescaler: 1200 MHz prescaler (64/65, 128/129)/500 MHz prescaler (8/9 or 16/17) • Serial input 14-bit programmable reference divider: R = 3 to 16,383 • Serial input programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 • Software selectable charge pump current • On-chip phase control for phase comparator • Operating temperature: Ta = –40 to +85°C • Pin compatible with MB15F02, MB15F02L
s PACKAGES
16-pin plastic SSOP 16-pad plastic BCC
(FPT-16P-M05)
(LCC-16P-M04)
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MB15F02SL
s PIN ASSIGNMENTS
16-pin SSOP
16-pad BCC
GNDRF OSCIN GNDIF finIF VCCIF LD/fout PSIF DOIF
1 2 3 4 5 6 7 8 TOP VIEW
16 15 14 13 12 11 10 9
Clock Data LE finRF VCCRF XfinRF PSRF DORF OSCIN GNDIF finIF VCCIF LD/fout PSIF 1 2 3 4 5 6
GNDRF Clock 16 15 14 13 TOP VIEW 12 11 10 7 8 9 Data LE finRF VCCRF XfinRF PSRF
DOIF DORF
(FPT-16P-M05)
(LCC-16P-M04)
2
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MB15F02SL
s PIN DESCRIPTIONS
Pin no. SSOP-16 BCC-16 1 2 3 4 5 16 1 2 3 4 Pin name GNDRF OSCIN GNDIF finIF VCCIF I/O – I – I – Ground for RF-PLL section. The programmable reference divider input. TCXO should be connected with a AC coupling capacitor. Ground for the IF-PLL section. Prescaler input pin for the IF-PLL. Connection to an external VCO should be via AC coupling. Power supply voltage input pin for the IF-PLL section. Lock detect signal output (LD)/phase comparator monitoring output (fout). The output signal is selected by LDS bit in a serial data. LDS bit = “H” ; outputs fout signal LDS bit = “L” ; outputs LD signal Power saving mode control for the IF-PLL section. This pin must be set at “L” during Power-ON. (Open is prohibited.) PSIF = “H” ; Normal mode PSIF = “L” ; Power saving mode Charge pump output for the IF-PLL section. Phase characteristics of the phase detector can be selected via programming of the FC-bit. Charge pump output for the RF-PLL section. Phase characteristics of the phase detector can be selected via programming of the FC-bit. Power saving mode control for the RF-PLL section. This pin must be set at “L” during Power-ON. (Open is prohibited.) PSRF = “H” ; Normal mode PSRF = “L” ; Power saving mode Prescaler complementary input for the RF-PLL section. This pin should be grounded via a capacitor. Power supply voltage input pin for the RF-PLL section, the shift register and the oscillator input buffer. When power is OFF, latched data of RF-PLL is lost. Prescaler input pin for the RF-PLL. Connection to an external VCO should be via AC coupling. Load enable signal inpunt (with a schmitt trigger input buffer.) When the LE bit is set “H”, data in the shift register is transferred to the corresponding latch according to the control bit in the serial data. Serial data input (with a schmitt trigger input buffer.) Data is transferred to the corresponding latch (IF-ref counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in the serial data. Clock input for the 23-bit shift register (with a schmitt trigger input buffer.) One bit of data is shifted into the shift register on a rising edge of the clock. Descriptions
6
5
LD/fout
O
7
6
PSIF
I
8
7
DoIF
O
9
8
DoRF
O
10
9
PSRF
I
11 12 13 14
10 11 12 13
XfinRF VCCRF finRF LE
I – I I
15
14
Data
I
16
15
Clock
I
3
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MB15F02SL
s BLOCK DIAGRAM
VCCIF GNDIF 5 (4) 3 (2)
PSIF 7 (6)
Intermittent mode control (IF-PLL)
3-bit latch
LDS SWIF FCIF
7-bit latch
Binary 7-bit swallow counter (IF-PLL)
11-bit latch
Binary 11-bit programmable counter (IF-PLL)
fpIF
Phase comp. (IF-PLL)
Charge pump Current (IF-PLL) Switch
8 DoIF (7)
finIF 4 (3)
Prescaler (IF-PLL) 8/9, 16/17
Lock Det. (IF-.