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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21350-1E
ASSP
Dual Serial Input
PLL FrequencySynthesizer MB15F03L
s DESCRIPITON
The Fujitsu MB15F03L is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1800MHz and a 250MHz prescalers. A 64/65 or a 128/129 for the 1800MHz prescaler, and a 16/17 or a 32/33 for 250MHz prescaler can be selected that enables pulse swallow operation. The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 5.0mA typ. at a supply voltage of 3.0V. Furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. As a result of this, MB15F03L is ideally suitable for digital mobile communications, such as PHS(Personal Handy Phone System), PCN (Personal Communication Network) and PCS(Personal Communication Service).
s FEATURES
• • • • • • • High frequency operation RF synthesizer: 1800MHz max. / IF synthesizer: 250MHz max. Low power supply voltage: VCC = 2.7 to 3.6V Very Low power supply current : ICC = 5.0 mA typ. (Vcc = 3V) Power saving function : Supply current at power saving mode Typ.0.1µA (Vcc=3V), Max.10µA (IPS1=IPS2) Dual modulus prescaler : 1800MHz prescaler(64/65,128/129) , 250MHz prescaler(16/17,32/33) Serial input 14–bit programmable reference divider: R = 5 to 16,383 Serial input 18–bit programmable divider consisting of: - Binary 7–bit swallow counter: 0 to 127 - Binary 11–bit programmable counter: 5 to 2,047 • On–chip high performance charge pump circuit and phase comparator, achieving high–speed lock–up and low phase noise • On–chip phase control for phase comparator • Wide operating temperature: Ta = -40 to 85°C
s PACKAGE
16-pin, Plastic SSOP 16-pin, Plastic BCC
(FPT-16P-M05)
(LCC-16P-M03)
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MB15F03L
s PIN ASSIGNMENT
SSOP-16-PIN
GNDRF OSCin GNDIF finIF VccIF LD/fout PSIF DoIF
1 2 3 4
16 15 14
Clock Data LE finRF VccRF XfinRF PSRF DoRF
TOP 13 VIEW 5 12 6 7 8 11 10 9
(FPT-16P-M05)
BCC-16-PIN
GNDRF Clock OSCin GNDIF finIF VCCIF LD/fout PSIF 1 2 3 16 15 14 13 12 Data LE finRF VCCRF XinRF PSRF
TOP VIEW
4 5 6 7 8 11 10 9
DOIF DORF
(LCC-16P-M03)
2
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MB15F03L
s PIN DESCRIPTION
Pin No. SSOP-16 1 2 3 4 5 BCC-16 16 1 2 3 4 Pin name GNDRF OSCin GNDIF finIF VccIF I/O – I – I – Ground for RF–PLL section. The programmable reference divider input. TCXO should be connected with a AC coupling capacitor. Ground for the IF-PLL section. Prescaler input pin for the IF-PLL. The connection with VCO should be AC coupling. Power supply voltage input pin for the IF-PLL section. Lock detect signal output (LD) / phase comparator monitoring output (fout) The output signal is selected by a LDS bit in a serial data. LDS bit = ”H” ; outputs fout signal LDS bit = ”L” ; outputs LD signal Power saving mode control for the IF-PLL section. This pin must be set at ”L” Power-ON. (Open is prohibited.) PSIF = ”H” ; Normal mode PSIF = ”L” ; Power saving mode Charge pump output for the IF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Charge pump output for the RF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Power saving mode control for the RF-PLL section. This pin must be set at ”L” Power-ON. (Open is prohibited.) PSRF = ”H” ; Normal mode PSRF = ”L” ; Power saving mode Prescaler complimentary input for the RF-PLL section. This pin should be grounded via a capacitor. Power supply voltage input pin for the RF-PLL section, the shift register and the oscillator input buffer. When power is OFF, latched data of RFPLL is cancelled. Prescaler input pin for the RF-PLL. The connection with VCO should be AC coupling. Load enable signal input (with the schmitt trigger circuit.) When LE is ”H”, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. Serial data input (with the schmitt trigger circuit.) A data is transferred to the corresponding latch (IF-ref counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data. Clock input for the 23-bit shift register (with the schmitt trigger circuit.) One bit data is shifted into the shift register on a rising edge of the clock. Descriptions
6
5
LD/fout
O
7
6
PSIF
I
8 9
7 8
DoIF DoRF
O O
10
9
PSRF
I
11 12 13
10 11 12
XfinRF VccRF finRF
I – I
14
13
LE
I
15
14
Data
I
16
15
Clock
I
3
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MB15F03L
s BLOCK DIAGRAM
VccIF
5
GNDIF
3
7
PSIF
Intermittent mode control
(IF–PLL)
3-bit latch LDS SWIF FCIF
7-bit latch
11-bit latch
fpIF
Binary 11-bit Binary 7-bit swallow counter programmable counter(IF–PLL) (IF–PLL)
Phase comp.
(IF–PLL)
Charge Super pump charger (IF–PLL)
8 DoIF
Prescaler
finIF 4
(IF–PLL)
16/17,32/33 2-bit latch T1 T2 14-bit latch
frIF Binary 14–bit programmable ref. counter(IF–PLL)
Lock Det.
(IF–PLL)
LDI
2
OSCin
AND OR
frRF
T1
T2
Binary 14-bit programmable ref. count.