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MB15F78UL Dataheets PDF



Part Number MB15F78UL
Manufacturers Fujitsu Media Devices
Logo Fujitsu Media Devices
Description Dual Serial Input PLL Frequency Synthesizer
Datasheet MB15F78UL DatasheetMB15F78UL Datasheet (PDF)

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS04-21369-1E ASSP Dual Serial Input PLL Frequency Synthesizer MB15F78UL s DESCRIPTION The Fujitsu MB15F78UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2600 MHz and a 1200 MHz prescalers. A 32/33 or a 64/65 for the 2600 MHz prescaler, and a 16/17 or a 32/33 for the 1200 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The BiCMOS process is used, as a result a supply current .

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www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS04-21369-1E ASSP Dual Serial Input PLL Frequency Synthesizer MB15F78UL s DESCRIPTION The Fujitsu MB15F78UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2600 MHz and a 1200 MHz prescalers. A 32/33 or a 64/65 for the 2600 MHz prescaler, and a 16/17 or a 32/33 for the 1200 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The BiCMOS process is used, as a result a supply current is typically 4.5 mA at 2.7 V. The supply voltage range is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial date. The data format is the same as the previous one MB15F08SL, MB15F78SP . Fast locking is achieved for adopting the new circuit. The new package (BCC20) decreases a mount area of MB15F78UL more than 30% comparing with the former BCC16 (for dual PLL) . MB15F78UL is ideally suited for wireless mobile communications, such as GSM and PCS. s FEATURES • High frequency operation : RX synthesizer : 2600 MHz Max. : TX synthesizer : 1200 MHz Max. • Low power supply voltage : VCC = 2.4 to 3.6 V • Ultra low power supply current : ICC = 4.5 mA Typ. (VCC = Vp = 2.7 V, Ta = +25 °C, SWTX = SWRX = 0, in TX/RX locking state) (Continued) s PACKAGES 20-pin plastic TSSOP 20-pad plastic BCC (FPT-20P-M06) (LCC-20P-M05) www.DataSheet4U.com MB15F78UL (Continued) • Direct power saving function : Power supply current in power saving mode Typ. 0.1 µA (VCC = Vp = 2.7 V, Ta = +25°C) Max. 10 µA (VCC = Vp = 2.7 V) • Software selectable charge pump current : 1.5 mA/6.0 mA Typ. • Dual modulus prescaler : 2600 MHz prescaler (32/33 or 64/65) /1200 MHz prescaler (16/17 or 32/33) • 23-bit shift register • Serial input binary 14-bit programmable reference divider : R = 3 to 16,383 • Serial input programmable divider consisting of : - Binary 7-bit swallow counter : 0 to 127 - Binary 11-bit programmable counter : 3 to 2,047 • Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit • On-chip phase control for phase comparator • On-chip phase comparator for fast lock and low noise • Built-in digital locking detector circuit to detect PLL locking and unlocking • Operating temperature : Ta = −40 to +85 °C • Serial data format compatible with MB15F08SL s PIN ASSIGNMENTS (TSSOP-20) TOP VIEW OSCIN GND finTX XfinTX GNDTX VCCTX PSTX VpTX DoTX LD/fout 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Clock Data LE finRX XfinRX GNDRX VCCRX PSRX VpRX DoRX finTX XfinTX GNDTX VCCTX PSTX VpTX 1 2 3 4 5 6 7 8 9 10 (BCC-20) TOP VIEW OSCIN Data GND Clock 20 19 18 17 16 15 14 13 12 11 LE finRX XfinRX GNDRX VCCRX PSRX DoRX DoTX LD/fout VpRX (FPT-20P-M06) (LCC-20P-M05) 2 www.DataSheet4U.com MB15F78UL s PIN DESCRIPTION Pin no. TSSOP 1 2 3 4 5 6 BCC 19 20 1 2 3 4 Pin name I/O OSCIN GND finTX XfinTX GNDTX VCCTX I Descriptions The programmable reference divider input pin. TCXO should be connected with an AC coupling capacitor. Prescaler input pin for the TX-PLL. Connection to an external VCO should be via AC coupling. Prescaler complimentary input pin for the TX-PLL section. This pin should be grounded via a capacitor. Power supply voltage input pin for the TX-PLL section (except for the charge pump circuit) , the oscillator input buffer and the shift register. Power saving mode control pin for the TX-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited.) PSTX = “H” ; Normal mode/PSTX = “L” ; Power saving mode Charge pump output pin for the TX-PLL section. Lock detect signal output (LD) /phase comparator monitoring output (fout) .The output signal is selected by LDS bit in the serial data. LDS bit = “H” ; outputs fout signal/LDS bit = “L” ; outputs LD signal Charge pump output pin for the RX-PLL section. Power saving mode control pin for the RX-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited.) PSRX = “H” ; Normal mode/PSRX = “L” ; Power saving mode Power supply voltage input pin for the RX-PLL section (except for the charge pump circuit) Prescaler complimentary input pin for the RX-PLL section. This pin should be grounded via a capacitor. Prescaler input pin for the RX-PLL. Connection to an external VCO should be via AC coupling. Load enable signal input pin (with the schmitt trigger circuit) When LE is set “H”, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. Serial data input pin (with the schmitt trigger circuit) Data is transferred to the corresponding latch (TX-ref. counter, TX-prog. counter, RX-ref.counter, RX-prog.counter) according to the control bit in a serial data. Clock input pin for the 23-bit shift register (with a schmitt trigger circuit) One bit of data is shifted into the shift register on a rising edge of the clock.  Ground pin for OSC input buffer and the shif.


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