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AD7612 Datasheet, Equivalent, approximation register.

16-bit charge redistribution successive approximation register

16-bit charge redistribution successive approximation register

 

 

 

Part AD7612
Description 16-bit charge redistribution successive approximation register
Feature 16-Bit, 750 kSPS, Unipolar/Bipolar Progr ammable Input PulSAR® ADC AD7612 FEATU RES Multiple pins/software programmable input ranges: 5 V, 10 V, ±5 V, ±10 V Pins or serial SPI®-compatible input ranges/mode selection Throughput 750 kS PS (warp mode) 600 kSPS (normal mode) 5 00 kSPS (impulse mode) INL: ±0.
75 LSB typical, ±1.
5 LSB maximum (±23 ppm of FSR) 16-bit resolution with no missing codes SNR: 92 minimum (5 V) @ 2 kHz, 9 4 dB typical (±10 V) @ 2 kHz THD: −1 07 dB typical iCMOS™ process technolo gy 5 V internal reference: typical drif t 3 ppm/°C; TEMP output No pipeline de lay (SAR architecture) Para .
Manufacture Analog Devices
Datasheet
Download AD7612 Datasheet
Part AD7612
Description 16-bit charge redistribution successive approximation register
Feature 16-Bit, 750 kSPS, Unipolar/Bipolar Progr ammable Input PulSAR® ADC AD7612 FEATU RES Multiple pins/software programmable input ranges: 5 V, 10 V, ±5 V, ±10 V Pins or serial SPI®-compatible input ranges/mode selection Throughput 750 kS PS (warp mode) 600 kSPS (normal mode) 5 00 kSPS (impulse mode) INL: ±0.
75 LSB typical, ±1.
5 LSB maximum (±23 ppm of FSR) 16-bit resolution with no missing codes SNR: 92 minimum (5 V) @ 2 kHz, 9 4 dB typical (±10 V) @ 2 kHz THD: −1 07 dB typical iCMOS™ process technolo gy 5 V internal reference: typical drif t 3 ppm/°C; TEMP output No pipeline de lay (SAR architecture) Para .
Manufacture Analog Devices
Datasheet
Download AD7612 Datasheet

AD7612

AD7612
AD7612

AD7612

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