dual inverter. 74AUP2G04 Datasheet

74AUP2G04 inverter. Datasheet pdf. Equivalent


Part 74AUP2G04
Description Low-power dual inverter
Feature 74AUP2G04 Low-power dual inverter Rev. 6 — 17 September 2015 Product data sheet 1. General descrip.
Manufacture NXP
Datasheet
Download 74AUP2G04 Datasheet


74AUP2G04 Low-power dual inverter Rev. 6 — 17 September 2015 74AUP2G04 Datasheet
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74AUP2G04
74AUP2G04
Low-power dual inverter
Rev. 6 — 17 September 2015
Product data sheet
1. General description
The 74AUP2G04 provides two inverting buffers.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 A (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C



74AUP2G04
NXP Semiconductors
74AUP2G04
Low-power dual inverter
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP2G04GW 40 C to +125 C SC-88
74AUP2G04GM 40 C to +125 C XSON6
74AUP2G04GF 40 C to +125 C XSON6
74AUP2G04GN 40 C to +125 C XSON6
74AUP2G04GS 40 C to +125 C XSON6
74AUP2G04GX 40 C to +125 C X2SON6
Description
Version
plastic surface-mounted package; 6 leads
SOT363
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 1.45 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 1 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
SOT1202
plastic thermal extremely thin small outline package; SOT1255
no leads; 6 terminals; body 1 0.8 0.35 mm
4. Marking
Table 2. Marking
Type number
74AUP2G04GW
74AUP2G04GM
74AUP2G04GF
74AUP2G04GN
74AUP2G04GS
74AUP2G04GX
Marking code[1]
p4
p4
p4
p4
p4
p4
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
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PQE
Fig 1. Logic symbol






PQE
Fig 2. IEC logic symbol
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PQD
Fig 3. Logic diagram
74AUP2G04
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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