56F802

56F802 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F802 Rev. 9 01/2007 freescale.com 56F802 General Description Up to 30 MIPS operation at 60MHz core frequency Up to 40 MIPS operation at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes Hardware DO and REP loops 6-channel PWM Module with fault input Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel) Serial Communications Interface (SCI) Two General Purpose Quad Timers with 2 external outputs 8K × 16-bit words (16KB) Program Flash 1K × 16-bit words (2KB) Program RAM 2K × 16-bit words (4KB) Data Flash 1K × 16-bit words (2KB) Data RAM 2K × 16-bit words (4KB) Boot Flash JTAG/OnCETM port for debugging On-chip relaxation oscillator 4 shared GPIO 32-pin LQFP Package 6 PWM Outputs Fault A0 PWMA 2 A/D1 3 A/D2 ADC VREF Interrupt Controller Quad Timer C Quad Timer D 2 or GPIO Program Memory 8188 x 16 Flash 1024 x 16 SRAM Boot Flash 2048x 16 Flash Data Memory 2048 x 16 Flash 1024 x 16 SRAM SCI0 2 or GPIO COP/ Watchdog Application-Specific Memory & Peripherals RESET 5 JTAG/ OnCE Port VCAPC VDD 22 VSS* VDDA 3 VSSA Digital Reg Analog Reg Low Voltage Supervisor Program Controller and Hardware Looping Unit Address Generation Unit Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers T...