MicroControllers. AT91FR40162S Datasheet

AT91FR40162S Datasheet PDF, Equivalent


Part Number

AT91FR40162S

Description

MicroControllers

Manufacture

ATMEL Corporation

Total Page 18 Pages
PDF Download
Download AT91FR40162S Datasheet PDF


AT91FR40162S Datasheet
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Features
Incorporates the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-circuit Emulation)
256K Bytes of On-chip SRAM
– 32-bit Data Bus, Single-clock Cycle Access
1024K Words 16-bit Flash Memory (2M bytes)
– Single Voltage Read/Write,
– Sector Erase Architecture
– Erase Suspend Capability
– Low-power Operation
– Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection
– Reset Input for Device Initialization
– Sector Program Unlock Command
– 128-bit Protection Register
– Factory-programmed AT91 Flash Memory Uploader Software
Fully Programmable External Bus Interface (EBI)
– Up to 8 Chip Selects, Maximum External Address Space of 64M Bytes
– Software Programmable 8/16-bit External Data Bus
8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
32 Programmable I/O Lines
3-channel 16-bit Timer/Counter
– 3 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel
2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
Programmable Watchdog Timer
Advanced Power-saving Features
– CPU and Peripherals Can be De-activated Individually
Fully Static Operation:
– 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85° C
2.7V to 3.6V I/O Operating Range, 1.65V to 1.95V Core Operating Range
-40° C to 85° C Temperature Range
Available in a 121-ball 10 x 10 x 1.2 mm BGA Package with 0.8 mm Ball Pitch
AT91 ARM®
Thumb®
Microcontrollers
AT91FR40162S
Summary
Preliminary
1. Description
The AT91FR40162S is a member of the Atmel AT91 16/32-bit Microcontroller family,
which is based on the ARM7TDMI processor core. The processor has a high-perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption.
The AT91FR40162S ARM microcontroller features 2 Mbits of on-chip SRAM and 2
Mbytes of Flash memory in a single compact 121-ball BGA package. Its high level of
integration and very small footprint make the device ideal for space-constrained appli-
cations. The high-speed on-chip SRAM enables a performance of up to 74 MIPs in
typical conditions with significant power reduction and EMC improvement over an
external SRAM implementation.
The Flash memory may be programmed via the JTAG/ICE interface or the factory-
programmed Flash Memory Uploader (FMU) using a single device supply, making the
AT91FR40162S suitable for in-system programmable applications.
6174AS–ATARM–25-May-05
DataSheet4 U .com

AT91FR40162S Datasheet
www.DataSheet4U.com
2. Pin Configuration
Figure 2-1. AT91FR40162S Pinout for 121-ball BGA Package (Top View)
A1 Corner
1
2
345678
9 10 11
P21/TXD1
NTRI
P19
P16
P15
RXD0
GND
P11
IRQ2
VDDCORE
P8
TIOB2
P6
TCLK2
GND
P2
TIOB0
P22
RXD1
P20
SCK1
P18
P17
P12
FIQ
P10
IRQ1
VDDIO
P7
TIOA2
P4
TIOA1
GND
P1
TIOA0
VDDIO
GND
NUB P14 NBUSY P9
NWR1 TXD0
IRQ0
P5 P3
TIOB1 TCLK1
A16
D15
P0
TCLK0
P23
MCKI
NRST
P13
SCK0
VPP NRSTF A14
A15
D12
D14 VDDIO
P24
BMS
P25
MCK0
NWDOVF
A3
A8
D11 D10 D13
NC
NC
D3
GND
TMS
GND
TCK
NOE
NRD
D9
A11
D7
D8
NC
NC
TDO
NWE
NWR0
A2
TDI NCS0 D2
D5
D4
D6 GND NC
P26
NCS2
VDDCORE VDDIO
NC
NCSF
NC
D0
D1
P31/A23
CS4
NC
NC
NWAIT
GND
P27
NCS3
A5
NC VDDIO GND
GND
A19
VDDIO
P30/A22
CS5
NCS1
NLB
A0
GND
A7 VDDIO A10
A13 GND A17 P2C9S/A621VDDCORE
GND
A1
A4
A6 VDDIO A9
A12 GND VDDIO A18
A20
A
B
C
D
E
F
G
H
J
K
L
2 AT91FR40162S
DataSheet4 U .com
6174AS–ATARM–25-May-05


Features Datasheet pdf www.DataSheet4U.com Features • Incorp orates the ARM7TDMI® ARM® Thumb® Pro cessor Core – High-performance 32-bit RISC Architecture – High-density 16- bit Instruction Set – Leader in MIPS/ Watt – Embedded ICE (In-circuit Emula tion) 256K Bytes of On-chip SRAM – 32 -bit Data Bus, Single-clock Cycle Acces s 1024K Words 16-bit Flash Memory (2M b ytes) – Single Voltage Read/Write, Sector Erase Architecture – Erase S uspend Capability – Low-power Operati on – Data Polling, Toggle Bit and Rea dy/Busy End of Program Cycle Detection – Reset Input for Device Initializati on – Sector Program Unlock Command 128-bit Protection Register – Facto ry-programmed AT91 Flash Memory Uploade r Software Fully Programmable External Bus Interface (EBI) – Up to 8 Chip Se lects, Maximum External Address Space o f 64M Bytes – Software Programmable 8 /16-bit External Data Bus 8-level Prior ity, Individually Maskable, Vectored In terrupt Controller – 4 External Interrupts, Including a High-priority Low-latency Interrupt Request .
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