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HDMI/DVI Transmitter. AD9889A Datasheet

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HDMI/DVI Transmitter. AD9889A Datasheet






AD9889A Transmitter. Datasheet pdf. Equivalent




AD9889A Transmitter. Datasheet pdf. Equivalent





Part

AD9889A

Description

High Performance HDMI/DVI Transmitter



Feature


www.DataSheet4U.com High Performance HD MI/DVI Transmitter AD9889A FEATURES Gen eral HDMITM/DVI transmitter compatible with HDMI v1.2a, DVI v1.0, and HDCP 1.1 Single 1.8 V power supply Video/audio inputs accept logic level s from 1.8 V to 3.3 V 76-ball CSP_BGA, Pb-free packa ge Digital video 80 MHz operation suppo rts all resolutions from 480i to 720p/1 080i and XGA-75 Hz.
Manufacture

Analog Devices

Datasheet
Download AD9889A Datasheet


Analog Devices AD9889A

AD9889A; Programmable two-way color space conver ter Supports RGB, YCbCr, DDR Supports I TU656 based embedded syncs Auto input v ideo format timing detection (CEA-861B) Digital audio Supports standard S/PDIF for stereo LPCM or compressed audio up to 192 kHz 8-channel uncompressed LPCM I2S audio up to 192 kHz Special featur es for easy system design On-chip MPU w ith I2C® master to.


Analog Devices AD9889A

perform HDCP operations and EDID readin g operations 5 V tolerant I2C and HPD I /Os, no extra device needed No audio ma ster clock needed for supporting S/PDIF and I2S On-chip MPU reports HDMI event s through interrupts and registers FUN CTIONAL BLOCK DIAGRAM SCL SDA MCL MDA I NT I2C SLAVE HDCP CORE REGISTER CONFIG URATION LOGIC INTERRUPT HANDLER HPD HDCP-EDID MICROCON.


Analog Devices AD9889A

TROLLER CLK VSYNC HSYNC DE D[23:0] VIDE O DATA CAPTURE COLOR SPACE CONVERSION 4 :2:2 TO 4:4:4 CONVERSION XOR MASK S/PDI F MCLK I2S[3:0] LRCLK SCLK AUDIO DATA C APTURE I2C MASTER DDCSDA DDCSCL Tx0[ 1:0] HDMI Tx CORE Tx1[1:0] Tx2[1:0] TxC [1:0] AD9889A 06148-001 Figure 1. AP PLICATIONS DVD players and recorders Di gital set-top boxes A/V receivers Digit al cameras and cam.

Part

AD9889A

Description

High Performance HDMI/DVI Transmitter



Feature


www.DataSheet4U.com High Performance HD MI/DVI Transmitter AD9889A FEATURES Gen eral HDMITM/DVI transmitter compatible with HDMI v1.2a, DVI v1.0, and HDCP 1.1 Single 1.8 V power supply Video/audio inputs accept logic level s from 1.8 V to 3.3 V 76-ball CSP_BGA, Pb-free packa ge Digital video 80 MHz operation suppo rts all resolutions from 480i to 720p/1 080i and XGA-75 Hz.
Manufacture

Analog Devices

Datasheet
Download AD9889A Datasheet




 AD9889A
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FEATURES
General
HDMITM/DVI transmitter compatible with HDMI v1.2a,
DVI v1.0, and HDCP 1.1
Single 1.8 V power supply
Video/audio inputs accept logic level s from 1.8 V to 3.3 V
76-ball CSP_BGA, Pb-free package
Digital video
80 MHz operation supports all resolutions from 480i to
720p/1080i and XGA-75 Hz
Programmable two-way color space converter
Supports RGB, YCbCr, DDR
Supports ITU656 based embedded syncs
Auto input video format timing detection (CEA-861B)
Digital audio
Supports standard S/PDIF for stereo LPCM or compressed
audio up to 192 kHz
8-channel uncompressed LPCM I2S audio up to 192 kHz
Special features for easy system design
On-chip MPU with I2C® master to perform HDCP
operations and EDID reading operations
5 V tolerant I2C and HPD I/Os, no extra device needed
No audio master clock needed for supporting S/PDIF
and I2S
On-chip MPU reports HDMI events through interrupts and
registers
APPLICATIONS
DVD players and recorders
Digital set-top boxes
A/V receivers
Digital cameras and camcorders
HDMI repeater/splitter
GENERAL DESCRIPTION
The AD9889A-BBCZ is an 80 MHz, high definition multimedia
interface (HDMI) v.1.2a transmitter. It supports HDTV formats
up to 720p/1080i, and computer graphic resolutions up to XGA
(1024 × 768 @ 75 Hz). With the inclusion of HDCP, the AD9889A
allows the secure transmission of protected content as specified
by the HDCP v1.1 protocol.
The AD9889A supports both S/PDIF and 8-channel I2S audio.
Its high fidelity 8-channel I2S can transmit either stereo or 7.1
surround audio at 192 kHz. The S/PDIF can carry stereo
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
DataSheet4 U .com
High Performance
HDMI/DVI Transmitter
AD9889A
FUNCTIONAL BLOCK DIAGRAM
SCL SDA
MCL MDA
INT
CLK
VSYNC
HSYNC
DE
D[23:0]
S/PDIF
MCLK
I2S[3:0]
LRCLK
SCLK
I2C
SLAVE
REGISTER
CONFIGURATION
LOGIC
HDCP
CORE
INTERRUPT
HANDLER
HDCP-EDID
MICRO-
CONTROLLER
I2C
MASTER
VIDEO
DATA
CAPTURE
COLOR
SPACE
CONVER-
SION
4:2:2 TO
4:4:4
CONVER-
SION
XOR
MASK
HDMI
Tx
CORE
AUDIO
DATA
CAPTURE
AD9889A
Figure 1.
HPD
DDCSDA
DDCSCL
Tx0[1:0]
Tx1[1:0]
Tx2[1:0]
TxC[1:0]
LPCM audio or compressed audio including Dolby® Digital,
DTS®, and THX®.
The AD9889A helps to reduce system design complexity and
cost by incorporating such features as an internal MPU for
HDCP operations, an I2C master for EDID reading, a single
1.8 V power supply and 5 V tolerance on I2C and hot plug
detect pins.
Fabricated in an advanced CMOS process, the AD9889A
is available in a space saving, 76-ball, CSP_BGA surface-
mount package. The CSP_BGA package is specified from
−25°C to +90°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.




 AD9889A
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AD9889A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Explanation of Test Levels ........................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Applications........................................................................................7
Design Resources ..........................................................................7
Document Conventions ...............................................................7
PCB Layout Recommendations.......................................................8
Power Supply Bypassing ...............................................................8
Digital Inputs .................................................................................8
External Swing Resistor................................................................8
Output Signals ...............................................................................8
Outline Dimensions ..........................................................................9
Ordering Guide..............................................................................9
REVISION HISTORY
10/06—Revision 0: Initial Version
DataSheet4 U .com
Rev. 0 | Page 2 of 12




 AD9889A
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AD9889A
SPECIFICATIONS
Table 1.
Parameter
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
THERMAL CHARACTERISTICS
Thermal Resistance
θJC Junction-to-Case
θJA Junction-to-Ambient
Ambient Temperature
DC SPECIFICATIONS
Input Leakage Current, IIL
Input Clamp Voltage
Differential High Level Output Voltage
Differential Output Short-Circuit Current
POWER SUPPLY
VDD (All) Supply Voltage
VDD Supply Voltage Noise
Power-Down Current
Transmitter Supply Current2
Transmitter Total Power
AC SPECIFICATIONS
CLK Frequency
TMDS Output CLK Duty Cycle
Worst Case CLK Input Jitter
Input Data Setup Time
Input Data Hold Time
TMDS Differential Swing
VSYNC and HSYNC Delay from DE Falling Edge
VSYNC and HSYNC Delay to DE Rising Edge
DE High Time
DE Low Time
Differential Output Swing
Low-to-High Transition Time
High-to-Low Transition Time
AUDIO AC TIMING
Sample Rate
I2S Cycle Time
I2S Setup Time
I2S Hold Time
Audio Pipeline Delay
Conditions
−16 mA
+16 mA
With active video applied
80 MHz, typical random pattern
I2S and S/PDIF
Temp
Full
Full
25°C
Full
Full
Full
25°C
25°C
25°C
Full
Full
25°C
25°C
Full
25°C
25°C
Full
Full
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Test Level1
VI
VI
V
VI
VI
V
V
V
VI
V
V
V
IV
IV
V
IV
IV
VI
IV
IV
IV
IV
IV
VI
VI
VI
VI
VI
VII
VII
IV
IV
IV
IV
IV
Min
1.4
VDD − 0.1
−25
−10
1.71
13.5
48
1
1
800
75
75
32
Typ
3
15.2
59
+25
−0.8
+0.8
AVCC
1.8
9
143
257
1000
1
1
138
15
0
75
Max
0.7
0.4
+90
+10
10
1.89
50
155
280
80
52
2
1200
8191
490
490
192
1
Unit
V
V
pF
V
V
°C/W
°C/W
°C
μA
V
V
V
μA
V
mV p-p
mA
mA
mW
MHz
%
ns
ns
ns
mV
UI3
UI
UI
UI
ps
ps
kHz
UI
ns
ns
μs
1 See Explanation of Test Levels section.
2 Using low output drive strength.
3 UI = unit interval.
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Rev. 0 | Page 3 of 12



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