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Embedded Processor. ADSP-21261 Datasheet

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Embedded Processor. ADSP-21261 Datasheet






ADSP-21261 Processor. Datasheet pdf. Equivalent




ADSP-21261 Processor. Datasheet pdf. Equivalent





Part

ADSP-21261

Description

SHARC Embedded Processor



Feature


SHARC Embedded Processor ADSP-21261/ADSP -21262/ADSP-21266 SUMMARY High perform ance 32-bit/40-bit floating-point proce ssor optimized for high performance aud io processing Code compatibility—at a ssembly level, uses the same instructio n set as other SHARC DSPs Processes hig h performance audio while enabling low system costs Audio decoders and postpro cessor algorithms su.
Manufacture

Analog Devices

Datasheet
Download ADSP-21261 Datasheet


Analog Devices ADSP-21261

ADSP-21261; pport nonvolatile memory that can be con figured to contain a combination of PCM 96 kHz, Dolby Digital, Dolby Digital S urround EX, DTS-ES Discrete 6.1, DTS-ES Matrix 6.1, DTS 96/24 5.1, MPEG2 AAC L C, MPEG2 BC 2ch, WMAPRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and DTS Neo:6 Various multichannel surround sou nd decoders are contained in ROM. For c onfigurations of d.


Analog Devices ADSP-21261

ecoder algorithms, see Table 3 on Page 4 . Single-instruction multiple-data (SI MD) computational architecture—two 32 -bit IEEE floating-point/32-bit fixed-p oint/ 40-bit extended precision floatin g-point computational units, each with a multiplier, ALU, shifter, and registe r file High bandwidth I/O—a parallel port, an SPI port, 6 serial ports, a Di gital application inte.


Analog Devices ADSP-21261

rface (DAI), and JTAG DAI incorporates t wo precision clock generators (PCGs), a n input data port (IDP) that includes a parallel data acquisition port (PDAP), and 3 programmable timers, all under s oftware control by the signal routing u nit (SRU) On-chip memory—up to 2M bit s on-chip SRAM and a dedicated 4M bits on-chip mask-programmable ROM The ADSP- 2126x processors are.

Part

ADSP-21261

Description

SHARC Embedded Processor



Feature


SHARC Embedded Processor ADSP-21261/ADSP -21262/ADSP-21266 SUMMARY High perform ance 32-bit/40-bit floating-point proce ssor optimized for high performance aud io processing Code compatibility—at a ssembly level, uses the same instructio n set as other SHARC DSPs Processes hig h performance audio while enabling low system costs Audio decoders and postpro cessor algorithms su.
Manufacture

Analog Devices

Datasheet
Download ADSP-21261 Datasheet




 ADSP-21261
SHARC
Embedded Processor
ADSP-21261/ADSP-21262/ADSP-21266
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
Processes high performance audio while enabling low
system costs
Audio decoders and postprocessor algorithms support
nonvolatile memory that can be configured to contain a
combination of PCM 96 kHz, Dolby Digital, Dolby Digital
Surround EX, DTS-ES Discrete 6.1, DTS-ES Matrix 6.1, DTS
96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA-
PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and
DTS Neo:6
Various multichannel surround sound decoders are con-
tained in ROM. For configurations of decoder algorithms,
see Table 3 on Page 4.
Single-instruction multiple-data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating-point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI port, 6 serial
ports, a Digital application interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an
input data port (IDP) that includes a parallel data acquisi-
tion port (PDAP), and 3 programmable timers, all under
software control by the signal routing unit (SRU)
On-chip memory—up to 2M bits on-chip SRAM and a dedi-
cated 4M bits on-chip mask-programmable ROM
The ADSP-2126x processors are available with a 150 MHz or a
200 MHz core instruction rate. For complete ordering
information, see Ordering Guide on Page 45.
CORE PROCESSOR
TIME R
INSTRUCTION
CACHE
32 ؋ 48-BIT
DAG1
DAG2
8 ؋ 4 ؋ 32 8 ؋ 4 ؋ 32
PROG RAM
SEQ UENCER
DUAL PORTED MEMORY
BLOCK 0
S RAM
1M BIT
ROM
2M BIT
ADDR
DATA
DUAL PORTED MEMORY
BLO CK 1
S RAM
1M BIT
ROM
2M BIT
ADDR
DATA
PM ADDRESS BUS
DM ADDRESS BUS
32
32
PROCES SING
ELEMENT
( PEX )
PRO CESSING
ELEMENT
( PE Y)
PX REGI STER
JTAG TEST & EMULATION
6
S
64 PM DATA BUS
64 DM DATA BUS
IOD IOA
(32) (19)
DMA CONTRO LLER
2 2 C HA N N ELS
4
SPI PORT (1)
SERIAL PORTS (6)
20 SIGNAL
RO UTI NG
UNI T
I NP UT
DATA PORTS (8)
PARALLEL DATA
ACQUISITION PORT
PRECISION CLOCK
GENERATORS (2)
3
PE RIPHERAL
TIMERS (3)
GPIO FLAGS/
IRQ /TIMEXP
4
IOP
RE GISTE RS
(MEMORY MAPPED)
CO NTROL,
S TATUS ,
DATA BUFFERS
AD D R ES S/
D A TA BU S / GPIO
CON TR OL/GPIO
P ARALLEL
P ORT
16
3
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. G
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




 ADSP-21261
ADSP-21261/ADSP-21262/ADSP-21266
TABLE OF CONTENTS
Summary ............................................................... 1
General Description ................................................. 3
Family Core Architecture ........................................ 3
Memory and I/O Interface Features ........................... 4
Target Board JTAG Emulator Connector .................... 8
Development Tools ............................................... 8
Additional Information .......................................... 9
Related Signal Chains ............................................ 9
Pin Function Descriptions ....................................... 10
Address Data Pins as Flags .................................... 13
Core Instruction Rate to CLKIN Ratio Modes ............ 13
Address Data Modes ............................................ 13
Product Specifications ............................................. 14
Operating Conditions .......................................... 14
Electrical Characteristics ....................................... 14
Package Information ........................................... 15
ESD Caution ...................................................... 15
Maximum Power Dissipation ................................. 15
Absolute Maximum Ratings ................................... 15
Timing Specifications ........................................... 15
Output Drive Currents ......................................... 37
Test Conditions .................................................. 37
Capacitive Loading .............................................. 37
Environmental Conditions .................................... 38
Thermal Characteristics ........................................ 38
144-Lead LQFP Pin Configurations ............................ 39
136-Ball BGA Pin Configurations ............................... 40
Outline Dimensions ................................................ 43
Surface-Mount Design .......................................... 44
Automotive Products .............................................. 45
Ordering Guide ..................................................... 45
REVISION HISTORY
12/12—Rev. F to Rev. G
Corrected Long Word Memory Space in Table 4 in
Memory and I/O Interface Features ...............................4
Updated Development Tools .......................................8
Added section, Related Signal Chains .............................9
Changed the package designator in Figure 36 from BC-136 to
BC-136-1. This change in no way affects form, fit, or function.
See Outline Dimensions ........................................... 43
Updated Ordering Guide .......................................... 45
Rev. G | Page 2 of 48 | December 2012




 ADSP-21261
ADSP-21261/ADSP-21262/ADSP-21266
GENERAL DESCRIPTION
The ADSP-21261/ADSP-21262/ADSP-21266 SHARC® DSPs
are members of the SIMD SHARC family of DSPs featuring
Analog Devices, Inc., Super Harvard Architecture. The
ADSP-2126x is source code compatible with the ADSP-21160
and ADSP-21161 DSPs as well as with first generation ADSP-
2106x SHARC processors in SISD (single-instruction, single-
data) mode. Like other SHARC DSPs, the ADSP-2126x are
32-bit/40-bit floating-point processors optimized for high per-
formance audio applications with dual-ported on-chip SRAM,
mask-programmable ROM, multiple internal buses to eliminate
I/O bottlenecks, and an innovative digital application interface.
Table 1 shows performance benchmarks for the processors run-
ning at 200 MHz. Table 2 shows the features of the individual
product offerings.
Table 1. Processor Benchmarks (at 200 MHz)
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with reversal)
FIR Filter (per tap)1
IIR Filter (per biquad)1
Matrix Multiply (pipelined)
[3×3] × [3×1]
[4×4] × [4×1]
Divide (y/x)
Inverse Square Root
1 Assumes two files in multichannel SIMD mode.
Speed
(at 200 MHz)
61.3 s
3.3 ns
13.3 ns
30 ns
53.3 ns
20 ns
30 ns
As shown in the functional block diagram in Figure 1 on Page 1,
the ADSP-2126x uses two computational units to deliver a 5 to
10 times performance increase over previous SHARC proces-
sors on a range of DSP algorithms. Fabricated in a state-of-the-
art, high speed, CMOS process, the ADSP-2126x DSPs achieve
an instruction cycle time of 5 ns at 200 MHz or 6.6 ns at
150 MHz. With its SIMD computational hardware, the
ADSP-2126x can perform 1200 MFLOPS running at 200 MHz,
or 900 MFLOPS running at 150 MHz.
Table 2. ADSP-2126x SHARC Processor Features
Feature
ADSP-21261 ADSP-21262 ADSP-21266
RAM
1M bit
2M bit
2M bit
ROM
3M bit
4M bit
4M bit
Audio Decoders No
in ROM1
No Yes
DMA Channels 18
22 22
SPORTs
4
66
Package
136-ball BGA 136-ball BGA 136-ball BGA
144-lead LQFP 144-lead LQFP 144-lead LQFP
1 For information on available audio decoding algorithms, see Table 3 on Page 4.
The ADSP-2126x continues the SHARC family’s industry-lead-
ing standards of integration for DSPs, combining a high
performance 32-bit DSP core with integrated, on-chip system
features. These features include 2M bit dual-ported SRAM
memory, 4M bit dual-ported ROM, an I/O processor that sup-
ports 22 DMA channels, six serial ports, an SPI interface,
external parallel bus, and digital application interface.
The block diagram of the ADSP-2126x on Page 1 illustrates the
following architectural features:
• Two processing elements, each containing an ALU, multi-
plier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
• Three programmable interval timers with PWM genera-
tion, PWM capture/pulse width measurement, and
external event counter capabilities
• On-chip dual-ported SRAM (up to 2M bit)
• On-chip dual-ported, mask-programmable ROM
(up to 4M bit)
• JTAG test access port
• 8- or 16-bit parallel port that supports interfaces to off-chip
memory peripherals
• DMA controller
• Six full-duplex serial ports (four on the ADSP-21261)
• SPI-compatible interface
• Digital application interface that includes two precision
clock generators (PCG), an input data port (IDP), six serial
ports, eight serial interfaces, a 20-bit synchronous parallel
input port, 10 interrupts, six flag outputs, six flag inputs,
three programmable timers, and a flexible signal routing
unit (SRU)
FAMILY CORE ARCHITECTURE
The ADSP-2126x is code compatible at the assembly level with
the ADSP-2136x and ADSP-2116x, and with the first generation
ADSP-2106x SHARC DSPs. The ADSP-2126x shares architec-
tural features with the ADSP-2136x and ADSP-2116x SIMD
SHARC family of DSPs, as detailed in the following sections.
SIMD Computational Engine
The ADSP-2126x contain two computational processing ele-
ments that operate as a single-instruction multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
and each contains an ALU, multiplier, shifter, and register file.
PEX is always active, and PEY can be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing
Rev. G | Page 3 of 48 | December 2012



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