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NB3N2304NZ Dataheets PDF



Part Number NB3N2304NZ
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description 3.3V 1:4 Clock Fanout Buffer
Datasheet NB3N2304NZ DatasheetNB3N2304NZ Datasheet (PDF)

NB3N2304NZ 3.3V 1:4 Clock Fanout Buffer Description The NB3N2304NZ is a low skew 1−to 4 clock fanout buffer, designed for high speed clock distribution such as in PCI−X applications. The NB3N2304NZ guarantees low output−to−output skew. Optimal design, layout and processing minimizes skew within a device and from device−to−device. The Output Enable (OE) pin forces the outputs LOW when LOW. Features • Input/Output Clock Frequency up to 140 MHz • Low Skew Outputs (100 ps) • Output Enable • Operati.

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NB3N2304NZ 3.3V 1:4 Clock Fanout Buffer Description The NB3N2304NZ is a low skew 1−to 4 clock fanout buffer, designed for high speed clock distribution such as in PCI−X applications. The NB3N2304NZ guarantees low output−to−output skew. Optimal design, layout and processing minimizes skew within a device and from device−to−device. The Output Enable (OE) pin forces the outputs LOW when LOW. Features • Input/Output Clock Frequency up to 140 MHz • Low Skew Outputs (100 ps) • Output Enable • Operating Range: VDD = 3.0 V to 3.6 V • Ideal for PCI−X and networking clocks • Packaged in 8−pin TSSOP, 4.4 mm x 3 mm • Industrial Temperature Range • These are Pb−Free Devices* http://onsemi.com MARKING DIAGRAM* TSSOP−8 DT SUFFIX CASE 948S 40N YWW AG 6O M 1 DFN8 MN SUFFIX CASE 506AA 14 A = Assembly Location Y = Year WW = Work Week M = Date Code G = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 October, 2009 − Rev. 6 1 Publication Order Number: NB3N2304NZ/D OE Logic Control Q1 Q2 IN Q3 Q4 Figure 2. Block Diagram NB3N2304NZ IN OE Q1 GND 1 2 3 4 8 Q4 7 Q3 6 VDD 5 Q2 Figure 3. NB3N2304NZ Package Pinout (Top View) Table 1. PIN DESCRIPTION Pin # Pin Name Type 1 IN LVCMOS/LVTTL Input 2 OE LVCMOS/LVTTL Input 3 Q1 LVCMOS/LVTTL Output 4 GND Power 5 Q2 (LV)CMOS/(LV)TTL Input 6 VDD Power 7 Q3 (LV)CMOS/(LV)TTL Output 8 Q4 (LV)CMOS/(LV)TTL Input − EP Thermal Exposed Pad Description Clock Input Output Enable for the clock outputs. Outputs are enabled when forced HIGH. Outputs are forced to logic LOW when OE is forced LOW. Clock Output 1 Negative Supply Voltage; Connect to Ground, 0 V Clock Output 2 Positive Supply Voltage (3.0 V to 3.6 V) Clock Output 3 Clock Output 4 (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Table 2. OE, OUTPUT ENABLE FUNCTION TABLE Inputs IN OE LL HL LH HH Outputs L L L H http://onsemi.com 2 NB3N2304NZ Table 3. ATTRIBUTES Characteristics ESD Protection Human Body Model Machine Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) TSSOP−8 DFN−8 Flammability Rating Oxygen Index: 28 to 34 Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Value > 2kV > 200 V Level 3 Level 1 UL 94 V−O @ 0.125 in 480 Devices Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VDD Positive Power Supply VI Input Voltage TA Operating Temperature Range, Industrial Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) GND = 0 V 0 lfpm 500 lfpm 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 DFN−8 DFN−8 VDD + 0.5V GND – 0.5 v VI v VDD + 0.5 w −40 to v +85 −65 to +150 143 103 129 84 V V °C °C °C/W TSOL Wave Solder Pb−Free (Note 2) 265 °C qJC Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) http://onsemi.com 3 NB3N2304NZ Table 5. DC CHARACTERISTICS VDD = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C Symbol Characteristic Min Typ Max Unit IDD Power Supply Current @ 66.66 MHz, Unloaded Outputs 12 25 mA VOH Output HIGH Voltage − IOH = −24 mA −IOH = −12 mA 2.0 2.4 V VOL Output LOW Voltage −IOL = 24 mA −IOL = 12 mA 0.8 V 0.55 VIH Input HIGH Voltage, IN and OE (Note 3) VIL Input LOW Voltage, IN and OE (Note 3) IIH Input HIGH Current, VIN = VDD IIL Input LOW Current, VIN = 0 V CIN Input Capacitance, IN, OE 2.0 −50 −100 5 V 0.8 V 50 mA 100 mA 7 pF NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. IN input has a threshold voltage of VDD/2. Table 6. AC CHARACTERISTICS VDD = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 4) (Figure 4) Symbol Characteristic Min Typ Max Unit .


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