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IDT72T1885 Dataheets PDF



Part Number IDT72T1885
Manufacturers IDT
Logo IDT
Description HIGH-SPEED TeraSync FIFO
Datasheet IDT72T1885 DatasheetIDT72T1885 Datasheet (PDF)

www.DataSheet4U.com 2.5 VOLT HIGH-SPEED TeraSync™ FIFO IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9, IDT72T18105, IDT72T18115 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9 IDT72T18125 FEATURES: • • • • • • • • • • • • • Choose among the following memory organizations: IDT.

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www.DataSheet4U.com 2.5 VOLT HIGH-SPEED TeraSync™ FIFO IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9, IDT72T18105, IDT72T18115 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9 IDT72T18125 FEATURES: • • • • • • • • • • • • • Choose among the following memory organizations: IDT72T1845  2,048 x 18/4,096 x 9 IDT72T1855  4,096 x 18/8,192 x 9 IDT72T1865  8,192 x 18/16,384 x 9 IDT72T1875  16,384 x 18/32,768 x 9 IDT72T1885  32,768 x 18/65,536 x 9 IDT72T1895  65,536 x 18/131,072 x 9 IDT72T18105  131,072 x 18/262,144 x 9 IDT72T18115  262,144 x 18/524,288 x 9 IDT72T18125  524,288 x 18/1,048,576 x 9 Up to 225 MHz Operation of Clocks User selectable HSTL/LVTTL Input and/or Output Read Enable & Read Clock Echo outputs aid high speed operation User selectable Asynchronous read and/or write port timing 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage 3.3V Input tolerant Mark & Retransmit, resets read pointer to user marked position Write Chip Select (WCS) input enables/disables Write operations Read Chip Select (RCS) synchronous to RCLK Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets Program programmable flags by either serial or parallel means Selectable synchronous/asynchronous timing modes for Almost- • • • • • • • • • • • • • • • Empty and Almost-Full flags Separate SCLK input for Serial programming of flag offsets User selectable input and output port bus-sizing - x9 in to x9 out - x9 in to x18 out - x18 in to x9 out - x18 in to x18 out Big-Endian/Little-Endian user selectable byte representation Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty, Full and Half-Full flags signal FIFO status Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts data outputs into high impedance state JTAG port, provided for Boundary Scan function Available in 144-pin (13mm x 13mm) or 240-pin (19mm x 19mm) PlasticBall Grid Array (PBGA) Easily expandable in depth and width Independent Read and Write Clocks (permit reading and writing simultaneously) High-performance submicron CMOS technology Industrial temperature range (–40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM D0 -Dn (x18 or x9) WEN WCLK/WR WCS LD SEN SCLK INPUT REGISTER OFFSET REGISTER FF/IR PAF EF/OR PAE HF FWFT/SI PFM FSEL0 FSEL1 ASYW WRITE CONTROL LOGIC RAM ARRAY 2,048 x 18 or 4,096 x 9 4,096 x 18 or 8,192 x 9 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9 32,768 x 18 or 65,536 x 9 65,536 x 18 or 131,072 x 9 131,072 x 18 or 262,144 x 9 262,144 x 18 or 524,288 x 9 524,288 x 18 or 1,048,576 x 9 FLAG LOGIC WRITE POINTER BE IP IW OW MRS PRS TCK TRST TMS TDO TDI Vref WHSTL RHSTL SHSTL CONTROL LOGIC BUS CONFIGURATION RESET LOGIC READ POINTER OUTPUT REGISTER READ CONTROL LOGIC RT MARK ASYR JTAG CONTROL (BOUNDARY SCAN) RCLK/RD REN RCS HSTL I/0 CONTROL OE EREN 5909 drw01 Q0 -Qn (x18 or x9) ERCLK IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1  2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. SEPTEMBER 2003 DSC-5909/16 IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/ 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATIONS A1 BALL PAD CORNER A WCS PRS MRS WHSTL LD FF/IR PAF OW HF BE IP ASYR PFM PAE EREN EF/OR REN RCS VDDQ MARK B WCLK FWFT/SI FSEL0 SHSTL FSEL1 DNC RHSTL RCLK RT OE C WEN VDDQ VDDQ VDDQ VCC VCC VDDQ VDDQ VDDQ D ASYW SEN IW VDDQ VCC VCC VCC GND GND VCC VCC GND VDDQ VCC E SCLK VDDQ GND GND GND GND Q17 F VREF D17 VCC VCC GND GND GND GND GND GND VCC VCC VDDQ VDDQ Q16 Q15 G D15 D16 GND GND GND GND GND GND GND GND GND GND H J D13 D14 VDDQ VCC VCC VCC VDDQ Q14 Q13 Q11 D11 D12 VDDQ VCC VDDQ GND VCC GND VCC VCC VDDQ VCC VDDQ VDDQ Q12 K D9 D10 VDDQ D3 D4 VDDQ VDDQ Q10 Q9 L D7 D5 D6 D1 D2 TRST D0 TCK TMS TDI TD0 ERCLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q7 M D8 1 NOTE: 1. DNC - Do Not Connect. 2 3 4 5 6 7 8 9 10 11 12 5909 drw02 IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895 Only PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB) TOP VIEW 2 IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/ 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 COMMERC.


IDT72T1875 IDT72T1885 IDT72T1895


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