IDT72T20108

www.DataSheet4U.com 2.5 VOLT HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION 32,768 x 20/65,536 x 10, 65,536 x 20/131,072 x 10 131,072 x 20/262,144 x 10, 262,144 x 20/524,288 x 10 IDT72T2098, IDT72T20108 IDT72T20118, IDT72T20128 FEATURES: Choose among the following memory organizations: IDT72T2098  32,768 x 20/65,536 x 10 IDT72T20108  65,536 x 20/131,072 x 10 IDT72T20118  131,072 x 20/262,144 x 10 IDT72T20128  262,144 x 20/524,288 x 10 Up to 250MHz Operation of Clocks - 4ns read/write cycle time, 3.2ns access time Users selectable input port to output port data rates, 500Mb/s Data Rate -DDR to DDR -DDR to SDR -SDR to DDR -SDR to SDR User selectable HSTL or LVTTL I/Os Read Enable & Read Clock Echo outputs aid high speed operation 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage 3.3V Input tolerant Mark & Retransmit, resets read pointer to user marked position Write Chip Select (WCS) input enables/disables Write Operations Read Chip Select (RCS) synchronous to RCLK Programmable Almost-Empty and Almost-Full flags, each flag can default to one of four preselected offsets Dedicated serial clock input for serial programming of flag offsets User selectable input and output port bus sizing -x20 in to x20 out -x20 in to x10 out -x10 in to x20 out -x10 in to x10 out Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains progra...