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IDT72T51256 Dataheets PDF



Part Number IDT72T51256
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES
Datasheet IDT72T51256 DatasheetIDT72T51256 Datasheet (PDF)

www.DataSheet4U.com ADVANCE INFORMATION 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits IDT72T51236 IDT72T51246 IDT72T51256 FEATURES: • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51236  Total Available Memory = 589,824 bits IDT72T51246  Total Available Memory = 1,179,648 bits IDT72T51256  Total Available Memory = 2,359,296 bits Configurable from 1 to 4 Queues Queues may be.

  IDT72T51256   IDT72T51256


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www.DataSheet4U.com ADVANCE INFORMATION 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits IDT72T51236 IDT72T51246 IDT72T51256 FEATURES: • • • • • • • • • • • • Choose from among the following memory density options: IDT72T51236  Total Available Memory = 589,824 bits IDT72T51246  Total Available Memory = 1,179,648 bits IDT72T51256  Total Available Memory = 2,359,296 bits Configurable from 1 to 4 Queues Queues may be configured at master reset from the pool of Total Available Memory in blocks of 256 x 36 Independent Read and Write access per queue User programmable via serial port User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL Default multi-queue device configurations -IDT72T51236: 4,096 x 36 x 4Q -IDT72T51246: 8,192 x 36 x 4Q -IDT72T51256: 16,384 x 36 x 4Q 100% Bus Utilization, Read and Write on every clock cycle 200 MHz High speed operation (5ns cycle time) 3.6ns access time Echo Read Enable & Echo Read Clock Outputs Individual, Active queue flags (OV, FF, PAE, PAF, PR) • • • • • • • • • • • • • 4 bit parallel flag status on both read and write ports Provides continuous PAE and PAF status of up to 4 Queues Global Bus Matching - (All Queues have same Input Bus Width and Output Bus Width) User Selectable Bus Matching Options: - x36in to x36out - x18in to x36out - x9in to x36out - x36in to x18out - x36in to x9out FWFT mode of operation on read port Packet mode operation Partial Reset, clears data in single Queue Expansion of up to 8 multi-queue devices in parallel is available Power Down Input provides additional power savings in HSTL and eHSTL modes. JTAG Functionality (Boundary Scan) Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm HIGH Performance submicron CMOS technology Industrial temperature range (-40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM MULTI-QUEUE FLOW-CONTROL DEVICE WADEN FSTR WRADD WEN WCLK 5 READ CONTROL RADEN ESTR RDADD 5 WRITE CONTROL Q0 REN RCLK EREN ERCLK OE x9, x18, x36 DATA IN FF PAF PAFn Din Qout x9, x18, x36 DATA OUT READ FLAGS OV PR PAE PAEn 4 PRn 6116 drw01 WRITE FLAGS Q3 4 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2003 DSC-6116/2 IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES DESCRIPTION: The IDT72T51236/72T51246/72T51256 multi-queue flow-control devices are single chip within which anywhere between 1 and 4 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user. Data writes and reads can be performed at high speeds up to 200MHz, with access times of 3.6ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously. The device provides Full flag and Output Valid flag status for the queue selected for write and read operations respectively. Also a Programmable Almost Full and Programmable Almost Empty flag for each queue is provided. Two 4 bit programmable flag busses are available, providing status of all queues, including queues not selected for write or read operations, these flag busses provide an individual flag per queue. Bus Matching is available on this device, either port can be 9 bits, 18 bits or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching is used the device ensures the logical transfer of data throughput in a Little Endian manner. A packet mode of operation is also provided when the device is configured for 36 bit input and 36 bit output port sizes. The Packet mode provides the user with a flag output indicating when at least one (or more) packets of data within a queue is available for reading. The Packet Ready provides the user with a means by which to mark the start and end of packets of data being passed through the queues. The multi-queue device then provides the user with an internally generated packet ready status per queue. The user has full flexibility configuring queues within the device, being able to program the total number of queues between 1 and 4, the individual queue depths being independent of each other. The programmable flag positions are also user programmable. All programming is done via a dedicated serial port. If the user does not wish to program the mult.


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