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CCD Area Image Sensor
MN39160FH
4.5 mm (type-1/4) 680k-pixel CCD Area Image Sensor
■ Overview
The MN39160FH is a 4.5 mm (type-1/4) interline transfer CCD (IT-CCD) solid state image sensor device. This device uses photodiodes in the optoelectric conversion section and CCDs for signal readout. The electronic shutter function has made an exposure time of 1/10 000 seconds possible. Further, this device has the features of high sensitivity, low noise, broad dynamic range, and low smear. This device has a total of 681 739 pixels (1 007 horizontal × 677 vertical) and provides stable and clear images with a resolution of 600 horizontal TV-lines and 420 vertical TV-lines. Part Number Size System NTSC Color or B/W Color
(Top View)
■ Pin Assignments
φV4 φV3 φV2 φV1 GND TEST VDD
1 2 3 4 5 6 7
14 13 12 11 10 9 8
PT Sub φH2 φH1 φR GND VO
MN39160FH 4.5 mm (type-1/4)
■ Features
• Effective pixel number 962 (horizontal) × 654 (vertical) • High sensitivity • Broad dynamic range • Low smear • Electronic shutter
■ Applications
• Camcorders • FA, OA cameras
Publication date: January 2003
SMD00002BEC
1
MN39160FH
■ Block Diagram
(4 columns OB + 962 columns valid area + 41 columns OB)
1
(2 dummies + OB11 + valid area 654 + OB12 )
Sub
13
φV4 2 φ V3 3 φ 4
V2
Photo diode
VO VDD GND
8 7 9
Output section
Vertical shift register
φV1
Horizontal register (one dummy at the front, no dummy at the back)
GND 6 TEST *1 14 PT
5
10
11 φH1
Description Pin No. Symbol 8 9 10 11 12
*1
φR
*1 : TEST pin must be left open, because the pin outputs CCD internal bias voltage.
■ Pin Descriptions
Pin No. Symbol 1 2 3 4 5 6 7 φV4 φV3 φV2 φV1 GND TEST VDD Description Video output GND Reset pulse (RG) Horizontal register clock pulse 1 Horizontal register clock pulse 2 Substrate P-well for protection circuit Vertical shift register clock pulse 4 Vertical shift register clock pulse 3 Vertical shift register clock pulse 2 Vertical shift register clock pulse 1 GND TEST pin (OPEN) Power supply VO GND φR φH1 φH2 Sub PT
13 14
Note) *1: TEST pin must be left open, because the pin outputs CCD internal bias volltage.
■ Device Parameter (H × V)
Parameter Pixel number
*1
Value 962 × 654 3.655 6 × 2.714 1 3.80 × 4.15
Unit pixel mm2 µ m2
Image sensing block dimension Pixel dimension
Note) *1: OB columns are not included.
2
SMD00002BEC
φH2
12
MN39160FH
■ Absolute Maximum Ratings and Operating Conditions
Absolute maximum rating Parameter VDD VPT
*3, 4
Operating condition Min 14.5 −7.5 3.0 Typ 15.0 −7.0 0 3.3 Max 15.5 −6.5 3.6 Unit V V V V V 3.3 0 3.3 0 3.6 0.2 3.6 0.2 V V V V V 22.0 15.0 0 −7.0 0 −7.0 15.0 0 −7.0 0 −7.0 25 23.0 15.5 0.05 −6.5 0.05 −6.5 15.5 0.05 −6.5 0.05 −6.5 V V V V V V V V V V V °C °C
Lower limit − 0.2 −10.0 − 0.2 − 0.2 − 0.2
Upper limit 18 0.2
GND VφR VφH1 VφH2 VSub
*2 *1
(Reference voltage) High-Low Bias High Low High Low 8 8 8
(Supplied internally) 3.0 − 0.2 3.0 − 0.2 (Supplied internally) 35 18 15 18 15 60 80 21.0 14.5 − 0.05 −7.5 − 0.05 −7.5 14.5 − 0.05 −7.5 − 0.05 −7.5 −9 −9 −9 −9 −10 −30
φVSub VφV1
*3, 4
High Middle Low
VφV2 VφV3
*3, 4
Middle Low
*3, 4
High Middle Low
VφV4
*3, 4
Middle Low
Operating temperature Storage temperature
SMD00002BEC
3
MN39160FH
■ Absolute Maximum Ratings and Operating Conditions (continued)
Note) 1. Standard photo detecting condition Standard photo detecting condition stands for detecting image with a light source of color temperature of 2 856K, luminance of 1 050 cd/m2, and using a color temperature conversion filter LB-40 (HOYA), infrared cut filter CAW-500S with thickness 2.5 mm for a light path and with F8 lens aperture. The quantity of the incidental light to a photo-detecting surface under the above condition is defined as the standard quantity of light. 2. *1: VSub when using electronic shutter function
φVSub H φVSub (V) φVSub L GND VSub (V) (Supplied internally)
* φSub pulse generates once every 1 V period.
*2: VSub supplied internally is the voltage suppressing the blooming generation at ×500 light quantity relative to the standard light quantity. *3: Relation between VPT and VφVL Set VPT under the following condition against VL of a vertical transfer clock waveform. VPT ≤ VL (VφV1L to VφV4L) − 0.2 < VφV − VPT < 24.5 (V) *4: Absolute maximum ratings
■ Optical Characteristics
Parameter Carrier saturation output Sensitivity Vertical smear Symbol Sc So Sm J chart J chart F1.4, 1/32 ND 1/10 V chart, F1.4 Conditions Min 500 80 Typ 110 Max 0.01 Unit mV mV %
Note) The above-mentioned characteristics are the values on driving the device for the imaging stabilizer mode (1/60 seconds accumulation).
4
SMD00002BEC
MN39160FH
■ Timing Diagram
• High speed pulse timing
φH1
50%
50%
50%
27.8 ns ± 3 ns
CCD output
φR
50%
50%
1 ns ± 3 ns
10 ns ∼ 13.9 ns
Clamp pulse (DS1)
50%
50%
3 ns ± 3 ns
13.9 ns ± 3 ns
Sampling pulse (DS2)
50%
50%
4 ns ± 3 ns
13.9 ns ± 3 ns
SMD00.