AND8001 COUNTERS Datasheet
ODD NUMBER DIVIDE BY COUNTERS
|Total Page||8 Pages|
Prepared by: Cleon Petty and Paul Shockman
The application inquiries handled by the Product
Applications gives opportunities to solve customer needs
with new ideas and learn of ways the customer has used our
devices in new applications. A couple of these calls lead to
techniques of designing odd number counters with
synchronous clocks and 50% outputs.
The first technique requires a differential clock, that has
a 50% duty cycle, a extra Flip Flop, and a gate to allow Odd
integers, such as 3, 5, 7, 9, to have 50% duty cycle outputs
and a synchronous clock. The frequency of operations is
limited by Tpd of the driving FF, Setup, and Hold of the extra
FF, and the times cannot exceed one half on the incoming
clock cycle time.
The design begins with producing a odd number counter
(Divide By 3 for this discussion) by any means one wishes
and add a flip flop, and a couple of gates to produce the
desired function. Karnaugh maps usually produce counters
that are lockup immune.
Divide By 3,
50% duty cycle on the output
50% duty cycle clock in
Using D type Flop flips and karnaugh maps we find;
Ad = A*B* and Bd = A
(Note: * indicates BAR function)
Figure 1 shows schematic and timing of such a design.
Divide By 3
© Semiconductor Components Industries, LLC, 1999
October, 1999 – Rev. 0
Publication Order Number:
Using the technique, we add a gate on the clock to get
differential Clock and Clock bar, a flip flop that triggers on
the Clock Bar rising edge (Clock Neg.) to shift the output of
”B” by 90 degrees and a gate to AND/OR two FF output to
produce the 50% output. We get Figure 2, a Divide By 3 that
clocks synchronously with 50% output duty cycle.
Divide By 3 W/50% out
The Max frequency of the configuration (figure 2) is
calculated as Clock input freq./2 = Tpd of FF ”B” + Setup
of ”C” + Hold of ”C”.
Tpd = 1Ns, Setup = !NS and Hold time = 0Ns.
with these numbers the Max Frequency the configuration
can expect is; Cycle time = 2*(1 + 1)Ns or 4 Ns that converts
The Method is usable on other divide by ”N” counters as
well by using the same methodology. The use of different
types of Flip Flops (J,K, S,R, Toggle, ETC.) may produce
fewer components. The type logic used may also dictate
configuration. The configuration should always be checked
for lockup conditions before the design is committed to a
A Divide By 3 design has all possible states shown in chart
1 but uses only the states shown in chart 2 leaving the states
2,3,4,5, & 7 for possible lockup.
|Features||www.DataSheet4U.com AND8001/D Odd Numbe r Divide By Counters With 50% Outputs a nd Synchronous Clocks Prepared by: Cleo n Petty and Paul Shockman Product Appli cations ON Semiconductor http://onsemi. com APPLICATION NOTE and add a flip fl op, and a couple of gates to produce th e desired function. Karnaugh maps usual ly produce counters that are lockup imm une. Example: The application inquirie s handled by the Product Applications g ives opportunities to solve customer ne eds with new ideas and learn of ways th e customer has used our devices in new applications. A couple of these calls l ead to techniques of designing odd numb er counters with synchronous clocks and 50% outputs. The first technique requi res a differential clock, that has a 50 % duty cycle, a extra Flip Flop, and a gate to allow Odd integers, such as 3, 5, 7, 9, to have 50% duty cycle outputs and a synchronous clock. The frequency of operations is limited by Tpd of the driving FF, Setup, and Hold of the extra FF, and the times can.|
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