BY COUNTERS. AND8001D Datasheet

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Part AND8001D
Description ODD NUMBER DIVIDE BY COUNTERS
Feature www.DataSheet4U.com AND8001/D Odd Number Divide By Counters With 50% Outputs and Synchronous Clocks.
Manufacture ON Semiconductor
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AND8001D
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AND8001/D
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Prepared by: Cleon Petty and Paul Shockman
Product Applications
ON Semiconductor
The application inquiries handled by the Product
Applications gives opportunities to solve customer needs
with new ideas and learn of ways the customer has used our
devices in new applications. A couple of these calls lead to
techniques of designing odd number counters with
synchronous clocks and 50% outputs.
The first technique requires a differential clock, that has
a 50% duty cycle, a extra Flip Flop, and a gate to allow Odd
integers, such as 3, 5, 7, 9, to have 50% duty cycle outputs
and a synchronous clock. The frequency of operations is
limited by Tpd of the driving FF, Setup, and Hold of the extra
FF, and the times cannot exceed one half on the incoming
clock cycle time.
The design begins with producing a odd number counter
(Divide By 3 for this discussion) by any means one wishes
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APPLICATION NOTE
and add a flip flop, and a couple of gates to produce the
desired function. Karnaugh maps usually produce counters
that are lockup immune.
Example:
Specify,
Divide By 3,
50% duty cycle on the output
Synchronous clocking
50% duty cycle clock in
Using D type Flop flips and karnaugh maps we find;
Ad = A*B* and Bd = A
(Note: * indicates BAR function)
Figure 1 shows schematic and timing of such a design.
DQ
A
Q
C
DQ
B
Q
C
Divide By 3
Figure 1.
© Semiconductor Components Industries, LLC, 1999
October, 1999 – Rev. 0
1
Publication Order Number:
AND8001/D



AND8001D
AND8001/D
Using the technique, we add a gate on the clock to get
differential Clock and Clock bar, a flip flop that triggers on
the Clock Bar rising edge (Clock Neg.) to shift the output of
”B” by 90 degrees and a gate to AND/OR two FF output to
produce the 50% output. We get Figure 2, a Divide By 3 that
clocks synchronously with 50% output duty cycle.
Clk in
DQ
A
Q
C
Clk
AQ
BQ
CQ
OUT
DQ
B
Q
C
DQ
C
Q
C
Divide By 3 W/50% out
Figure 2.
50% Out
The Max frequency of the configuration (figure 2) is
calculated as Clock input freq./2 = Tpd of FF ”B” + Setup
of ”C” + Hold of ”C”.
Example:
Tpd = 1Ns, Setup = !NS and Hold time = 0Ns.
with these numbers the Max Frequency the configuration
can expect is; Cycle time = 2*(1 + 1)Ns or 4 Ns that converts
to 250MHZ.
The Method is usable on other divide by ”N” counters as
well by using the same methodology. The use of different
types of Flip Flops (J,K, S,R, Toggle, ETC.) may produce
fewer components. The type logic used may also dictate
configuration. The configuration should always be checked
for lockup conditions before the design is committed to a
production.
Example:
A Divide By 3 design has all possible states shown in chart
1 but uses only the states shown in chart 2 leaving the states
2,3,4,5, & 7 for possible lockup.
Chart 1
ABC
0000
1100
2010
3110
4001
5101
6011
7111
Chart 2
ABC
0000
1100
6011
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2







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