AND8066 Interfacing Datasheet

AND8066 Datasheet PDF, Equivalent


Part Number

AND8066

Description

Interfacing

Manufacture

ON Semiconductor

Total Page 8 Pages
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AND8066
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AND8066/D
Interfacing with ECLinPS
Prepared by: Paul Shockman
ON Semiconductor Logic Applications Engineering
STANDARD ECL INTERFACE: DIFFERENTIAL
DRIVER AND RECEIVER
A typical Emitter Coupled Logic (ECL) circuit interface
may be defined as a differential driver device sending a paired
set of commentary signals – True and Invert – over a pair of
standard, controlled impedance lines to an ECL differential
receiver device. A typical ECL output line driver consists of
a bipolar transistor in an Emitter Follower configuration with
the collector at VCC power supply rail and the emitter pinned
out. A standard, typical differential ECL receiver consists of
a pair of bipolar transistors in a differential configuration with
the True and Invert signals providing base drives to the two
base inputs. Proper differential levels are specified as Vpp and
VIHCMR. When an input is interconnected as a differential
signal, the DC Single Ended parameters of VIL and VIH do not
apply. Terminations are required to preserve optimum signal
integrity, as shown in Figure 1. The standard, controlled
impedance lines assume a sufficient return current capability.
VCC
Q
True
VCC
DQ
Q
VEE
Invert
DQ
VEE
VTT
Figure 1. Standard Differential ECL Interconnect
SINGLE–ENDED INTERFACE
Signals may be imported as full differential lines or as a
Single–Ended (SE) line interconnection. The SE
interconnection may be seen as a special variation of the
typical differential interface using only one driver source
trace line. This single trace line drives a (Base) input pin of
the receiver, as shown in Figure 2. Although a receiver may
present only a single, dedicate SE input pin instead of a
differential input pair of pins, such a receiver still would have
a differential structure with the unavailable input controlled
by internal circuitry.
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APPLICATION NOTE
VCC
True
VCC
VEE
VEE
VTT
Figure 2. Standard Single–Ended ECL Interconnect
Single–ended receiver input levels are specified in data
sheets DC CHARACTERISTICS block as VIH and VIL
Parameters. Each temperature has a minimum and
maximum limit pair to VIH and VIL parameters, thus
defining the Single–Ended input swing, Vpp(SE). The
Vpp(SE) ranges from 595 mV to 890 mV, depending on the
temperature and family. The Vpp(SE) limits constitute the
receiver device’s input single–ended sensitivity.
Both output lines of the typical differential output may
drive two independent single–ended receivers separately (see
Figure 3).
VCC
VCC
Q
Q
VEE
True
Invert
Q
VEE
VTT
VCC
Q
VTT VEE
Figure 3. Differential Driver with Independent
Standard Single–Ended Receivers
© Semiconductor Components Industries, LLC, 2002
May, 2002 – Rev. 2
1
Publication Order Number:
AND8066/D

AND8066
AND8066/D
VBB Reference
For a standard differential receiver with two input pins –
D and D – only one of two inputs is suitably selected to
receive the signal while the non–driven input must be biased
to a (DC) reference voltage, VBB (see Figure 4).
VCC
Q
VEE
True
VTT
D
VCC
Q
VBB D
Q
VEE
Figure 4. Standard SE Receivers with VBB
The VBB value is designed to be maintained midway
(50%) between the HIGH and LOW levels of the received
signal, that is, the crosspoint voltage of a differential signal
pair, to preserve the duty cycle and signal integrity (see
Figure 5).
Invert
True
HIGH
VBB or Crosspoint
LOW
Figure 5. VBB Crosspoint Voltage
If VBB shifts, due to drift or noise, above the input signal
50% crosspoint, the device output signal will shift the duty
cycle away from a pure 50% point to a decreased, narrowing
pulse width (see Figure 6).
DVBB
Input
HIGH
DVBB
Input
HIGH
Output Shift Wider
Figure 7.
LOW
Obviously, any error voltage present on the VBB reference
level injects jitter directly into the signal.
VBB: Voltage Reference Sources
A VBB reference voltage output source pin may be available
on the receiver device. When present, VBB is an internally
generated voltage supply and available only to that device’s
inputs. Current demand on the VBB pin should be limited to 0.5
mA. Bypass (0.01 mF) VBB to the quietest plane, usually VCC,
since noise on VBB will inject jitter and corrupt duty cycle. The
VBB voltage is derived from referencing the VCC supply and
will track changes in VCC 100% or 1:1. If VCC shifts 1 mV,
then VBB also changes 1 mV. Changes in VEE also affect the
VBB voltage and will track at the rate of 0 to 20%, typically 5%.
If VEE shifts 100 mV, then VBB follows with a 0 mV to 20 mV
shift of the same polarity, typically 5 mV.
A VBB reference voltage may be generated off–device and
supplied to the input pins. Ripple content must be kept as low
as possible on VCC since it transfers to the signal as jitter and
phase error. A VBB voltage reference level may be supplied
from a VBB generator, as shown in Figure 8. Any of the “16”
type buffers are recommended to produce a high current gain
VBB buffer. For example, the E416, EL16, LVEL16, EP16,
LVEP16, EL17, LVEL17, etc. type devices have a VBB pin
available. A 1 KW resistor may be needed the feedback path
to stabilize higher gain buffers.
1 KW
LOW
Output Shift Narrower
Figure 6.
If VBB shifts below the input signal 50% crosspoint, the
device output signal will shift the duty cycle away from a
pure 50% point to an increased, widening pulse width (see
Figure 7).
16
VBB
VBB(out)
RT
0.01 mF
VTT
VCC or VTT
Figure 8. VBB Voltage Reference Generator
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2


Features www.DataSheet4U.com AND8066/D Interfaci ng with ECLinPS Prepared by: Paul Shock man ON Semiconductor Logic Applications Engineering http://onsemi.com APPLIC ATION NOTE STANDARD ECL INTERFACE: DIFF ERENTIAL DRIVER AND RECEIVER A typical Emitter Coupled Logic (ECL) circuit int erface may be defined as a differential driver device sending a paired set of commentary signals – True and Invert – over a pair of standard, controlled impedance lines to an ECL differential receiver device. A typical ECL output line driver consists of a bipolar trans istor in an Emitter Follower configurat ion with the collector at VCC power sup ply rail and the emitter pinned out. A standard, typical differential ECL rece iver consists of a pair of bipolar tran sistors in a differential configuration with the True and Invert signals provi ding base drives to the two base inputs . Proper differential levels are specif ied as Vpp and VIHCMR. When an input is interconnected as a differential signal, the DC Single Ended param.
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