CY7C1352

www.DataSheet4U.com CY7C1352 256K x18 Pipelined SRAM with NoBL™ Architecture Features Pin compatible and functionally equivalent to ZBT™ devices MCM63Z818 and MT55L256L18P Supports 143-MHz bus operations with zero wait states — Data is transferred on every clock Internally self-timed output buffer control to eliminate the need to use OE Fully registered (inputs and outputs) for pipelined operation Byte Write Capability 256K x 18 common I/O architecture Single 3.3V power supply Fast clock-to-output times — 4.0 ns (for 143-MHz device) — 4.2 ns (for 133-MHz device) — 5.0 ns (for 100-MHz device) — 7.0 ns (for 80-MHz device) Clock Enable (CEN) pin to suspend operation Synchronous self-timed writes Asynchronous output enable JEDEC-standard 100-pin TQFP package Burst Capability—linear or interleaved burst order Low standby power Functional Description The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Read/Write transitions.The CY7C1352 is pin/functionally compatible to ZBT™ SRAMs MCM63Z819 and MT55L256L18P. All synchronous inputs pass thro...