IS42S16400

www.DataSheet4U.com IS42S16400 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES Clock frequency: 166, 133, 100 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Single 3.3V power supply LVTTL interface Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Self refresh modes 4096 refresh cycles every 64 ms Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Byte controlled by LDQM and UDQM Industrial temperature availability Package: 400-mil 54-pin TSOP II ISSI FINAL PRODUCTION MAY 2001 ® OVERVIEW ISSI's 64Mb Synchronous DRAM IS42S16400 is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. PIN CONFIGURATIONS 54-Pin TSOP (Type II) VCC I/O0 VCCQ I/O1 I/O2 GNDQ I/O3 I/O4 VCCQ I/O5 I/O6 GNDQ I/O7 VCC LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 GND I/O15 GNDQ I/O14 I/O13 VCCQ I/O12 I/O11 GNDQ I/O10 I/O9 VCCQ I/O8 GND NC UDQM CLK CK...