ADSP-TS101S Processor Datasheet

ADSP-TS101S Datasheet PDF, Equivalent


Part Number

ADSP-TS101S

Description

TigerSHARC Embedded Processor

Manufacture

Analog Devices

Total Page 30 Pages
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Download ADSP-TS101S Datasheet PDF


ADSP-TS101S
FEATURES
300 MHz, 3.3 ns instruction cycle rate
6M bits of internal—on-chip—SRAM memory
19 mm × 19 mm (484-ball) or 27 mm × 27 mm
(625-ball) PBGA package
Dual computation blocks—each containing an ALU, a multi-
plier, a shifter, and a register file
Dual integer ALUs, providing data addressing and pointer
manipulation
Integrated I/O includes 14-channel DMA controller, external
port, 4 link ports, SDRAM controller, programmable flag
pins, 2 timers, and timer expired pin for system integration
1149.1 IEEE compliant JTAG test access port for on-chip
emulation
On-chip arbitration for glueless multiprocessing with up to
8 TigerSHARC processors on a bus
TigerSHARC
Embedded Processor
ADSP-TS101S
BENEFITS
Provides high performance Static Superscalar DSP opera-
tions, optimized for telecommunications infrastructure
and other large, demanding multiprocessor DSP
applications
Performs exceptionally well on DSP algorithm and I/O bench-
marks (see benchmarks in Table 1 and Table 2)
Supports low overhead DMA transfers between internal
memory, external memory, memory-mapped peripherals,
link ports, other DSPs (multiprocessor), and host
processors
Eases DSP programming through extremely flexible instruc-
tion set and high-level language-friendly DSP architecture
Enables scalable multiprocessing systems with low commu-
nications overhead
COMPUTATIONAL BLOCKS
SHIFTER
ALU
MULTIPLIER
X
REGISTER
FILE
32 × 32
128 128
DAB
DAB
128 128
Y
REGISTER
FILE
32 × 32
MULTIPLIER
ALU
SHIFTER
PROGRAM SEQUENCER
PC BTB IRQ
ADDR
IAB FETCH
DATA ADDRESS GENERATION
INTEGER 32
J ALU
32 × 32
32 INTEGER
K ALU
32 × 32
32
128
32
128
32
128
I/O PROCESSOR
DMA
CONTROLLER
CONTROL/
STATUS/
TCBs
DMA ADDRESS
DMA DATA
INTERNAL MEMORY
MEMORY MEMORY MEMORY
M0 M1 M2
64K × 32 64K × 32 64K × 32
A DA DA D
6
JTAG PORT
SDRAM CONTROLLER
32 256
M0 ADDR
M0 DATA
M1 ADDR
M1 DATA
EXTERNAL PORT
MULTIPROCESSOR
INTERFACE
HOST INTERFACE
INPUT FIFO
32
ADDR
64
OUTPUT BUFFER
DATA
M2 ADDR
M2 DATA
I/O ADDRESS 32
OUTPUT FIFO
CLUSTER BUS
ARBITER
CNTRL
3
LINK PORT
CONTROLLER
L0 8
3
256 LINK DATA
L1
LINK
PORTS
8
3
CONTROL/
STATUS/
BUFFERS
L2 8
3
L3 8
Figure 1. Functional Block Diagram
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2009 Analog Devices, Inc. All rights reserved.

ADSP-TS101S
ADSP-TS101S
TABLE OF CONTENTS
Features ................................................................. 1
Benefits ................................................................. 1
Table of Contents ..................................................... 2
Revision History ...................................................... 2
General Description ................................................. 3
Dual Compute Blocks ............................................ 4
Data Alignment Buffer (DAB) .................................. 4
Dual Integer ALUs (IALUs) .................................... 4
Program Sequencer ............................................... 5
On-Chip SRAM Memory ........................................ 5
External Port
(Off-Chip Memory/Peripherals Interface) ................ 6
DMA Controller ................................................... 7
Link Ports ........................................................... 9
Timer and General-Purpose I/O ............................... 9
Reset and Booting ................................................. 9
Low Power Operation ............................................ 9
Clock Domains .................................................... 9
Output Pin Drive Strength Control ......................... 10
Power Supplies ................................................... 10
Filtering Reference Voltage and Clocks .................... 10
Development Tools ............................................. 10
REVISION HISTORY
5/09—Rev. B to Rev. C
Added parameter value (IDD_A max) in
Operating Conditions ............................................. 20
Updated footnotes in 484-Ball PBGA (B-484) ............... 43
Updated footnotes in 625-Ball PBGA (B-625) ............... 44
Added surface-mount design info
in Surface-Mount Design ......................................... 44
Updated models in Ordering Guide ............................ 45
Designing an Emulator-Compatible
DSP Board (Target) .......................................... 11
Additional Information ........................................ 11
Pin Function Descriptions ........................................ 12
Pin States at Reset ................................................ 12
Pin Definitions ................................................... 12
Strap Pin Function Descriptions ................................ 19
Specifications ........................................................ 20
Operating Conditions ........................................... 20
Electrical Characteristics ....................................... 20
Absolute Maximum Ratings ................................... 21
ESD Caution ...................................................... 21
Package Information ............................................ 21
Timing Specifications ........................................... 21
Output Drive Currents ......................................... 32
Test Conditions .................................................. 34
Environmental Conditions .................................... 36
PBGA Pin Configurations ........................................ 37
Outline Dimensions ................................................ 43
Surface-Mount Design ............................................. 44
Ordering Guide ..................................................... 45
Rev. C | Page 2 of 48 | May 2009


Features www.DataSheet4U.com a KEY FEATURES 300 MHz, 3.3 ns Instruction Cycle Rate 6M B its of Internal—On-Chip—SRAM Memory 19 mm ؋ 19 mm (484-Ball) or 27 mm ؋ 27 mm (625-Ball) PBGA Package Dual Comp utation Blocks—Each Containing an ALU , a Multiplier, a Shifter, and a Regist er File Dual Integer ALUs, Providing Da ta Addressing and Pointer Manipulation Integrated I/O Includes 14 Channel DMA Controller, External Port, Four Link Po rts, SDRAM Controller, Programmable Fla g Pins, Two Timers, and Timer Expired P in for System Integration 1149.1 IEEE C ompliant JTAG Test Access Port for On-C hip Emulation On-Chip Arbitration for G lueless Multiprocessing with up to Eigh t TigerSHARC Processors on a Bus Embed ded Processor ADSP-TS101S KEY BENEFITS Provides High Performance Static Supers calar DSP Operations, Optimized for Tel ecommunications Infrastructure and Othe r Large, Demanding Multiprocessor DSP A pplications Performs Exceptionally Well on DSP Algorithm and I/O Benchmarks (See Benchmarks in Table 1 and Tab.
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