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ADSP-TS201S Dataheets PDF



Part Number ADSP-TS201S
Manufacturers Analog Devices
Logo Analog Devices
Description TigerSHARC-R Embedded Processor
Datasheet ADSP-TS201S DatasheetADSP-TS201S Datasheet (PDF)

www.DataSheet4U.com Preliminary Technical Data KEY FEATURES Up to 600 MHz, 1.67 ns Instruction Cycle Rate 24M Bits of Internal—On-Chip—DRAM Memory 25×25 mm (576-Ball) Thermally Enhanced Ball Grid Array Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, a Register File, and a Communications Logic Unit (CLU) Dual Integer ALUs, providing Data Addressing and Pointer Manipulation Integrated I/O Includes 14 Channel DMA Controller, External Port, Four Link Ports, SDRAM Co.

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www.DataSheet4U.com Preliminary Technical Data KEY FEATURES Up to 600 MHz, 1.67 ns Instruction Cycle Rate 24M Bits of Internal—On-Chip—DRAM Memory 25×25 mm (576-Ball) Thermally Enhanced Ball Grid Array Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, a Register File, and a Communications Logic Unit (CLU) Dual Integer ALUs, providing Data Addressing and Pointer Manipulation Integrated I/O Includes 14 Channel DMA Controller, External Port, Four Link Ports, SDRAM Controller, Programmable Flag Pins, Two Timers, and Timer Expired Pin for System Integration 1149.1 IEEE Compliant JTAG Test Access Port for On-Chip Emulation On-Chip Arbitration for Glueless Multiprocessing TigerSHARC® Embedded Processor ADSP-TS201S KEY BENEFITS Provides High-Performance Static Superscalar DSP Operations, Optimized for Telecommunications Infrastructure and Other Large, Demanding Multiprocessor DSP Applications Performs Exceptionally Well on DSP Algorithm and I/O Benchmarks (See Benchmarks in Table 1) Supports Low-Overhead DMA Transfers Between Internal Memory, External Memory, Memory-Mapped Peripherals, Link Ports, Host Processors, and Other (Multiprocessor) DSPs Eases DSP Programming Through Extremely Flexible Instruction Set and High-Level-Language Friendly DSP Architecture Enables Scalable Multiprocessing Systems With Low Communications Overhead DATA ADDRESS GENERATION INTEGER J ALU PROGRAM SEQUENCER ADDR FETCH J-BUS ADDR J-BUS DATA K-BUS ADDR BTB K-BUS DATA I-BUS ADDR PC I-BUS DATA 32X32 32 32 INTEGER K ALU 32X32 32 24M BITS INTERNAL MEMORY MEMORY BLOCKS (PAGE CACHE) 4xCROSSBAR CONNECT A D A D A D A D SOC BUS JTAG JTAG PORT 6 EXTERNAL PORT 32 ADDR HOST MULTI PROC SDRAM CTRL 64 DATA 8 CTRL 10 CTRL 128 32 SOC INTERFACE 128 32 128 S-BUS ADDR S-BUS DATA 128 32 C-BUS ARB EXT DMA REQ 4 DMA LINK PORTS 4 8 4 OUT 8 4 8 IN 4 OUT 8 4 8 IN 4 OUT 8 4 8 IN 4 OUT 8 IN IAB T MULTIPLIER L0 L1 X REGISTER FILE 32x32 MULTIPLIER 128 128 DAB DAB 128 128 Y REGISTER FILE 32x32 L2 SHIFTER SHIFTER ALU CLU ALU CLU L3 COMPUTATIONAL BLOCKS Figure 1. Functional block diagram TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc. Rev. PrH Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel:781/329-4700 www.analog.com Fax:781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADSP-TS201S TABLE OF CONTENTS General Description ................................................. 3 Dual Compute Blocks ..................


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