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56F8347/56F8147
Data Sheet Preliminary Technical Data
56F8300 16-bit Hybrid Controllers
MC56F8347 Rev. 3.0 10/2004
freescale.com
Document Revision History
Version History Rev 0 Rev 1.0 Initial release Fixed typos in Section 1.1.3, Replace any reference to Flash Interface Unit with Flash Module, corrected pin number for D14 in Table 2-2, added note to Vcap pin in Table 2-2, corrected thermal numbers for 160 LQFP in Table 10-4,removed unneccessary notes in Table 10-13; corrected temperature range in Table 10-14; added ADC calibration information to Table 10-24 and new graphs in Figure 10-22. Clarification to Table 10-23, corrected Digital Input Current Low (pull-up enabled) numbers in Table 10-5. Removed text and Table 10-2; replaced with note to Table 10-1. Added 56F8147 information; edited to indicate differences in 56F8347 and 56F8147. Reformatted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then updaated balance of electrical tables for consistency throughout the family. Clarified I/O power description in Table 2-2, added note to Table 10-7 and clarified Section 12.3. Description of Change
Rev 2.0 Rev 3.0
Please see http://www.freescale.com/semiconductors for the most current Data Sheet revision.
56F8347 Technical Data, Rev. 3.0 2 Freescale Semiconductor Preliminary
56F8347/56F8147 General Description
Note: Features in italics are NOT available in the 56F8147 device.
• Up to 60 MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Access up to 4MB of off-chip program and 32MB of data memory • Chip Select Logic for glueless interface to ROM and SRAM • 128KB of Program Flash • 4KB of Program RAM • 8KB of Data Flash • 8KB of Data RAM • 8KB of Boot Flash • Up to two 6-channel PWM modules • Four 4-channel, 12-bit ADCs • Temperature Sensor • Up to two Quadrature Decoders • FlexCAN module • Two Serial Communication Interfaces (SCIs) • Up to two Serial Peripheral Interfaces (SPIs) • Up to four general-purpose Quad Timers • Computer Operating Properly (COP) / Watchdog • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Up to 76 GPIO lines • 160-pin LQFP Package
RSTO
EMI_MODE EXTBOOT 5 JTAG/ EOnCE Port
VPP 2
VCAP* 4
OCR_DIS VDD VSS 7 6 Digital Reg
VDDA 2
VSSA
RESET 6 3 4 6 3 4 4 4 5 4 4 PWM Outputs
* Configuration shown for on-chip 2.5V regulator
PWMA
Analog Reg
Current Sense Inputs or GPIOC Fault Inputs PWM Outputs
16-Bit 56800E Core
Low Voltage Supervisor
Bit Manipulation Unit
PWMB
Current Sense Inputs or GPIOD Fault Inputs AD0 AD1 VREF AD0 AD1
Program Controller and Hardware Looping Unit
Address Generation Unit
Data ALU 16 x 16 + 36 Æ 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators
ADCA
PAB PDB CDBR CDBW
ADCB
Memory
Program Memory 64K x 16 Flash 2K x 16 RAM Boot ROM 4K x 16 Flash
R/W Control XDB2 XAB1 XAB2 PAB PDB CDBR CDBW
6 2
External Address Bus Switch
A0-5 or GPIOA8-13 A6-7 or GPIOE2-3 A8-15 or GPIOA0-7 GPIOB0-3 (A16-19) GPIOB4 (A20, prescaler_clock) GPIOB5-7 (A21-23, clk0-3**) D0-6 or GPIOF9-15 D7-15 or GPIOF0-8 WR RD
Temp_Sense Quadrature Decoder 0 or Quad Timer A or GPIOC Quadrature Decoder 1 or Quad Timer B or SPI1 or GPIOC Quad Timer C or GPIOE Quad Timer D or GPIOE FlexCAN
8 4 1 3
4
Data Memory
4K x 16 RAM 4K x 16 Flash
External Bus Interface Unit
System Bus Control
External Data Bus Switch
7 9
4
IPBus Bridge (IPBB)
Peripheral Device Selects
RW Control IPAB IPWDB IPRDB
Bus Control
6
GPIOD0-5 or CS2-7 PS (CS0 or GPIOD8) DS (CS1 or GPIOD9) **See Table 2-2 for explanation
2
Decoding Peripherals
Clock resets PLL
2 2
SPI0 or GPIOE 4
SCI1 or GPIOD 2
SCI0 or GPIOE 2
COP/ Watchdog
Interrupt Controller
P System O Integration R Module
O Clock S Generator C
XTAL EXTAL
IRQA
IRQB
CLKO
CLKMODE
56F8347/56F8147 Block Diagram
56F8347 Technical Data, Rev. 3.0 Freescale Semiconductor Preliminary 3
Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8347/56F8147 Features . . . . . . . . . . . . . 5 Device Description . . . . . . . . . . . . . . . . . . . . 7 Award-Winning Development Environment . 9 Architecture Block Diagram . . . . . . . . . . . . 10 Product Documentation . . . . . . . . . . . . . . . 14 Data Sheet Conventions . . . . . . . . . . . . . . 14
Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . 128
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 128 8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 128 8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . 128
Part 9: Joint Test Action Group (JTAG) . 133
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . .133
Part 2: Signal/Connection Descriptions . . . 15
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
Part 10: Sp.