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Clock Generators. MAX9450 Datasheet

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Clock Generators. MAX9450 Datasheet






MAX9450 Generators. Datasheet pdf. Equivalent




MAX9450 Generators. Datasheet pdf. Equivalent





Part

MAX9450

Description

High-Precision Clock Generators



Feature


www.DataSheet4U.com 19-0547; Rev 2; 9/0 6 High-Precision Clock Generators with Integrated VCXO General Description Th e MAX9450/MAX9451/MAX9452 clock generat ors provide high-precision clocks for t iming in SONET/SDH systems or Gigabit E thernet systems. The MAX9450/ MAX9451/M AX9452 can also provide clocks for the highspeed and high-resolution ADCs and DACs in 3G base st.
Manufacture

Maxim Integrated Products

Datasheet
Download MAX9450 Datasheet


Maxim Integrated Products MAX9450

MAX9450; ations. Additionally, the devices can al so be used as a jitter attenuator for g enerating high-precision CLK signals. T he MAX9450/MAX9451/MAX9452 feature an i ntegrated VCXO. This configuration elim inates the use of an external VCXO and provides a cost-effective solution for generating high-precision clocks. The M AX9450/MAX9451/ MAX9452 feature two dif ferential inputs a.


Maxim Integrated Products MAX9450

nd clock outputs. The inputs accept LVPE CL, LVDS, differential signals, and LVC MOS. The input reference clocks range f rom 8kHz to 500MHz. The MAX9450/MAX9451 /MAX9452 offer LVPECL, HSTL, and LVDS o utputs, respectively. The output range is up to 160MHz, depending on the selec tion of crystal. The input and output f requency selection is implemented throu gh the I 2 C or SP.


Maxim Integrated Products MAX9450

I™ interface. The MAX9450/ MAX9451/MAX 9452 feature clock output jitter less t han 0.8ps RMS (in a 12kHz to 20MHz band ) and phasenoise attenuation greater th an -130dBc/Hz at 100kHz. The phase-lock ed loop (PLL) filter can be set externa lly, and the filter bandwidth can vary from 1Hz to 20kHz. The MAX9450/MAX9451/ MAX9452 feature an input clock monitor with a hitless switc.

Part

MAX9450

Description

High-Precision Clock Generators



Feature


www.DataSheet4U.com 19-0547; Rev 2; 9/0 6 High-Precision Clock Generators with Integrated VCXO General Description Th e MAX9450/MAX9451/MAX9452 clock generat ors provide high-precision clocks for t iming in SONET/SDH systems or Gigabit E thernet systems. The MAX9450/ MAX9451/M AX9452 can also provide clocks for the highspeed and high-resolution ADCs and DACs in 3G base st.
Manufacture

Maxim Integrated Products

Datasheet
Download MAX9450 Datasheet




 MAX9450
www.DataSheet4U.com
19-0547; Rev 2; 9/06
High-Precision Clock Generators
with Integrated VCXO
General Description
The MAX9450/MAX9451/MAX9452 clock generators
provide high-precision clocks for timing in SONET/SDH
systems or Gigabit Ethernet systems. The MAX9450/
MAX9451/MAX9452 can also provide clocks for the high-
speed and high-resolution ADCs and DACs in 3G base
stations. Additionally, the devices can also be used as a
jitter attenuator for generating high-precision CLK signals.
The MAX9450/MAX9451/MAX9452 feature an integrated
VCXO. This configuration eliminates the use of an exter-
nal VCXO and provides a cost-effective solution for gen-
erating high-precision clocks. The MAX9450/MAX9451/
MAX9452 feature two differential inputs and clock out-
puts. The inputs accept LVPECL, LVDS, differential sig-
nals, and LVCMOS. The input reference clocks range
from 8kHz to 500MHz.
The MAX9450/MAX9451/MAX9452 offer LVPECL, HSTL,
and LVDS outputs, respectively. The output range is up
to 160MHz, depending on the selection of crystal. The
input and output frequency selection is implemented
through the I2C or SPI™ interface. The MAX9450/
MAX9451/MAX9452 feature clock output jitter less than
0.8ps RMS (in a 12kHz to 20MHz band) and phase-
noise attenuation greater than -130dBc/Hz at 100kHz.
The phase-locked loop (PLL) filter can be set externally,
and the filter bandwidth can vary from 1Hz to 20kHz.
The MAX9450/MAX9451/MAX9452 feature an input
clock monitor with a hitless switch. When a failure is
detected at the selected reference clock, the device
can switch to the other reference clock. The reaction to
the recovery of the failed reference clock can be
revertive or nonrevertive. If both reference clocks fail,
the PLL retains its nominal frequency within a range of
±20ppm at +25°C.
The MAX9450/MAX9451/MAX9452 operate from 2.4V to
3.6V supply and are available in 32-pin TQFP packages
with exposed pads.
Applications
SONET/SDH Systems
10 Gigabit Network Routers and Switches
3G Cellular Phone Base Stations
General Jitter Attenuation
Features
Integrated VCXO Provides a Cost-Effective
Solution for High-Precision Clocks
8kHz to 500MHz Input Frequency Range
15MHz to 160MHz Output Frequency Range
I2C or SPI Programming for the Input and Output
Frequency Selection
PLL Lock Range > ±60ppm
Two Differential Outputs with Three Types of
Signaling: LVPECL, LVDS, or HSTL
Input Clock Monitor with Hitless Switch
Internal Holdover Function within ±20ppm of the
Nominal Frequency
Low Output CLK Jitter: < 0.8ps RMS in the 12kHz
to 20MHz Band
Low Phase Noise > -130dBc at 100kHz, > -140dBc
at 1MHz
Ordering Information
PART
PIN-PACKAGE OUTPUT PKG CODE
MAX9450EHJ 32 TQFP-EP*
LVPECL
H32E-6
MAX9451EHJ 32 TQFP-EP*
HSTL
H32E-6
MAX9452EHJ 32 TQFP-EP*
LVDS
H32E-6
Note: All devices are specified over the -40°C to +85°C
temperature range.
For lead-free packages, contact factory.
*EP = Exposed paddle.
Pin Configuration
TOP VIEW
24 23 22 21 20 19 18 17
VDD 25
X1 26
X2 27
VDDA 28
LP1 29
LP2 30
GNDA 31
RJ 32
MAX9450
MAX9451
MAX9452
EXPOSED PAD
(GND)
16 CMON
15 AD1
14 AD0
13 SDA
12 SCL
11 GND/CS
10 MR
9 INT
123 45 67 8
SPI is a trademark of Motorola, Inc.
TQFP
(5mm x 5mm)
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.




 MAX9450
High-Precision Clock Generators
with Integrated VCXO
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +4.0V
VDDA to GNDA ......................................................-0.3V to +4.0V
All Other Pins to GND ...................................-0.3V to VDD + 0.3V
Short-Circuit Duration (all pins) ..................................Continuous
Continuous Power Dissipation (TA = +85°C)
32-Pin TQFP (derate 27.8mW/°C above +70°C)........2222mW
Storage Temperature Range .............................-65°C to +165°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection
Human Body Model (RD = 1.5k, CS = 100pF) ..............±2kV
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VDDA = VDD = VDDQ = 2.4V to 3.6V, and VDDQ = 1.4V to 1.6V for MAX9451, TA = -40°C to +85°C. Typical values at VDDA = VDD =
VDDQ = 3.3V, and VDDQ = 1.5V for MAX9451, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
LVCMOS INPUT (SEL_, CMON, OE, MR)
CONDITIONS
Input High Level
VIH1
Input Low Level
VIL1
Input Current
LVCMOS OUTPUT (INT, LOCK)
IIN1 VIN = 0V to VDD
Output High Level
VOH1 IOH1 = -4mA
Output Low Level
THREE-LEVEL INPUT (AD0, AD1)
Input High Level
Input Low Level
Input Open Level
Input Current
DIFFERENTIAL INPUTS (IN0, IN1)
Differential Input High Threshold
Differential Input Low Threshold
VOL1 IOL1 = 4mA
VIH2
VIL2
VIO2
IIL2, IIH2
Measured at the opened inputs
VIL2 = 0V or VIH2 = VDD
VIDH
VIDL
VID = VIN+ - VIN-
VID = VIN+ - VIN-
Common-Mode Input-Voltage Range
VCOM VID = VIN+ - VIN-
Input Current
IIN+, IIN-
MAX9450 OUTPUTS (CLK0, CLK1) (LVPECL)
Output High Voltage
VOH2 50load connected to VDDQ - 2.0V
Output Low Voltage
VOL2 50load connected to VDDQ - 2.0V
MAX9451 OUTPUTS (CLK0, CLK1) (differential HSTL)
Output High-Level Voltage
VOH3 With 50load resistor to GND, Figure 1
Output Low-Level Voltage
VOL3
MAX9452 OUTPUTS (CLK0, CLK1) (LVDS)
Differential Output Voltage
Change in VOD Between
Complementary Output States
VOD
VOD
With 50to GND and 16mA sink current
With a total 100load, Figure 1
MIN
2.0
0
-50
VDD
- 0.4
1.8
1.05
-15
-50
|VID / 2|
-1
VDDQ
- 1.42
VDDQ
- 2.15
VDDQ
- 0.4V
300
TYP MAX UNITS
VDD
V
0.8 V
+50 µA
V
0.4 V
V
0.8 V
1.35 V
+15 µA
50
2.4
- |VID / 2|
+1
mV
mV
V
µA
VDDQ
- 1.00
VDDQ
- 1.70
V
V
VDDQ
0.4
V
V
370 450
10 35
mV
mV
2 _______________________________________________________________________________________




 MAX9450
High-Precision Clock Generators
with Integrated VCXO
DC ELECTRICAL CHARACTERISTICS (continued)
(VDDA = VDD = VDDQ = 2.4V to 3.6V, and VDDQ = 1.4V to 1.6V for MAX9451, TA = -40°C to +85°C. Typical values at VDDA = VDD =
VDDQ = 3.3V, and VDDQ = 1.5V for MAX9451, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output Offset Voltage
VOS
Change in VOS Between
Complementary Output States
VOS
Output Short-Circuit Current
IOS Two output pins connected to GND
SERIAL INTERFACE INPUT, OUTPUT (SCL, SDA, CS)
Input High Level
VIH
Input Low Level
Input Leakage Current
Output Low Level
Input Capacitance
POWER CONSUMPTION
VDD and VDDA Supply Current
VDDQ Supply Current
VIL
IIL
VOL 3mA sink current
CI
ICC1
ICC2
Output clock
frequency =
155MHz
Output clock
frequency =
155MHz (MAX9450)
MAX9450
MAX9451
MAX9452
MAX9450
MAX9451
MAX9452
1.05 1.2 1.35
V
10 35 mV
-7.5 -15
mA
0.7
x VDD
0.3
x VDD
V
V
-1 +1 µA
0.4 V
10 pF
55 85
70 94 mA
65 88
55 80
65 80 mA
14 25
AC ELECTRICAL CHARACTERISTICS
(VDDA = VDD = VDDQ = 2.4V to 3.6V, and VDDQ = 1.4V to 1.6V for MAX9451, TA = -40°C to +85°C. |VID| = 200mV, VCOM = |VID / 2| to
2.4 - |VID / 2|. Typical values at VDDA = VDD = VDDQ = 3.3V and VDDQ = 1.5V for MAX9451, TA = +25°C. CL = 10pF, clock output =
155.5MHz and clock input = 19.44MHz, unless otherwise noted.) (Note 1)
PARAMETER
CLK OUTPUTS (CLK0, CLK1)
Reference Input Frequency
Output Frequency
VCXO Pulling Range
Output-to-Output Skew
Rise Time
Fall Time
Duty Cycle
Period Jitter (RMS)
Phase Noise
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
fIN
fOUT
tSKO
tR
tF
TJ
Measured at IN0 or IN1
Measured at CLK0 or CLK1
CL = 8pF (Note 2)
Skew between CLK0 and CLK1
(MAX9450 and MAX9452)
Skew between CLK0 and CLK1 (MAX9451)
20% to 80% of output swing
80% to 20% of output swing
Measured at the band 12kHz to 20MHz
1kHz offset
10kHz offset
100kHz offset
1MHz offset
0.008
15
43
50
55
0.4
0.4
0.8
-70
-110
-130
-140
500
160
±60
90
106
0.590
0.590
56
MHz
MHz
ppm
ps
ns
ns
%
ps
dBc
_______________________________________________________________________________________ 3



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