ADSP-21020

www.DataSheet4U.com a FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution 100 MFLOPS Peak, 66 MFLOPS Sustained Performance 1024-Point Complex FFT Benchmark: 0.58 ms Divide (y/x): 180 ns Inverse Square Root (1/√x ): 270 ns 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats 32-Bit Fixed-Point Formats, Integer and Fractional, with 80-Bit Accumulators IEEE Exception Handling with Interrupt on Exception Three Independent Computation Units: Multiplier, ALU, and Barrel Shifter Dual Data Address Generators with Indirect, Immediate, Modulo, and Bit Reverse Addressing Modes Two Off-Chip Memory Transfers in Parallel with Instruction Fetch and Single-Cycle Multiply & ALU Operations Multiply with Add & Subtract for FFT Butterfly Computation Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup Single-Cycle Register File Context Switch 15 (or 25) ns External RAM Access Time for Zero-WaitState, 30 (or 40) ns Instruction Execution IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation Circuitry 223-Pin PGA Package (Ceramic) GENERAL DESCRIPTION 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FUNCTIONAL BLOCK DIAGRAM DATA ADDRESS GENERATORS DAG 1 DAG 2 INSTRUCTION CACHE PROGRAM SEQUENCER JTAG TEST & EMULATION PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS EXTERNAL ADDRESS BUSES PROGR...