ADSP-21020 Microprocessor Datasheet

ADSP-21020 Datasheet, PDF, Equivalent

Part Number



32/40-Bit IEEE Floating-Point DSP Microprocessor


Analog Devices

Total Page 30 Pages
Download ADSP-21020 Datasheet

32/40-Bit IEEE Floating-Point
DSP Microprocessor
Superscalar IEEE Floating-Point Processor
Off-Chip Harvard Architecture Maximizes Signal
Processing Performance
30 ns, 33.3 MIPS Instruction Rate, Single-Cycle
100 MFLOPS Peak, 66 MFLOPS Sustained Performance
1024-Point Complex FFT Benchmark: 0.58 ms
Divide (y/x): 180 ns
Inverse Square Root (1/x): 270 ns
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats
32-Bit Fixed-Point Formats, Integer and Fractional,
with 80-Bit Accumulators
IEEE Exception Handling with Interrupt on Exception
Three Independent Computation Units: Multiplier,
ALU, and Barrel Shifter
Dual Data Address Generators with Indirect, Immedi-
ate, Modulo, and Bit Reverse Addressing Modes
Two Off-Chip Memory Transfers in Parallel with
Instruction Fetch and Single-Cycle Multiply & ALU
Multiply with Add & Subtract for FFT Butterfly
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Single-Cycle Register File Context Switch
15 (or 25) ns External RAM Access Time for Zero-Wait-
State, 30 (or 40) ns Instruction Execution
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation Circuitry
223-Pin PGA Package (Ceramic)
The ADSP-21020 is the first member of Analog Devices’ family
of single-chip IEEE floating-point processors optimized for
digital signal processing applications. Its architecture is similar
to that of Analog Devices’ ADSP-2100 family of fixed-point
DSP processors.
Fabricated in a high-speed, low-power CMOS process, the
ADSP-21020 has a 30 ns instruction cycle time. With a high-
performance on-chip instruction cache, the ADSP-21020 can
execute every instruction in a single cycle.
The ADSP-21020 features:
Independent Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter
perform single-cycle instructions. The units are architecturally
arranged in parallel, maximizing computational throughput. A
single multifunction instruction executes parallel ALU and
multiplier operations. These computation units support IEEE
32-bit single-precision floating-point, extended precision
40-bit floating-point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is used for transferring
data between the computation units and the data buses, and
for storing intermediate results. This 10-port (16-register)
register file, combined with the ADSP-21020’s Harvard
architecture, allows unconstrained data flow between
computation units and off-chip memory.
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-21020 uses a modified Harvard architecture in
which data memory stores data and program memory stores
both instructions and data. Because of its separate program
and data memory buses and on-chip instruction cache, the
processor can simultaneously fetch an operand from data
memory, an operand from program memory, and an
instruction from the cache, all in a single cycle.
Memory Interface
Addressing of external memory devices by the ADSP-21020 is
facilitated by on-chip decoding of high-order address lines to
generate memory bank select signals. Separate control lines
are also generated for simplified addressing of page-mode
The ADSP-21020 provides programmable memory wait
states, and external memory acknowledge controls allow
interfacing to peripheral devices with variable access times.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

Instruction Cache
The ADSP-21020 includes a high performance instruction
cache that enables three-bus operation for fetching an
instruction and two data values. The cache is selective—only
the instructions whose fetches conflict with program memory
data accesses are cached. This allows full-speed execution
of core, looped operations such as digital filter multiply-
accumulates and FFT butterfly processing.
Hardware Circular Buffers
The ADSP-21020 provides hardware to implement circular
buffers in memory, which are common in digital filters and
Fourier transform implementations. It handles address
pointer wraparound, reducing overhead (thereby increasing
performance) and simplifying implementation. Circular
buffers can start and end at any location.
Flexible Instruction Set
The ADSP-21020’s 48-bit instruction word accommodates a
variety of parallel operations, for concise programming. For
example, the ADSP-21020 can conditionally execute a
multiply, an add, a subtract and a branch in a single
The ADSP-21020 is supported with a complete set of software
and hardware development tools. The ADSP-21000 Family
Development System includes development software, an
evaluation board and an in-circuit emulator.
Creates relocatable, COFF (Common Object File Format)
object files from ADSP-21xxx assembly source code. It
accepts standard C preprocessor directives for conditional
assembly and macro processing. The algebraic syntax of the
ADSP-21xxx assembly language facilitates coding and
debugging of DSP algorithms.
The Linker processes separately assembled object files and
library files to create a single executable program. It assigns
memory locations to code and to data in accordance with a
user-defined architecture file that describes the memory and
I/O configuration of the target system. The Librarian allows
you to group frequently used object files into a single library
file that can be linked with your main program.
The Simulator performs interactive, instruction-level
simulation of ADSP-21xxx code within the hardware
configuration described by a system architecture file. It flags
illegal operations and supports full symbolic disassembly. It
provides an easy-to-use, window oriented, graphical user
interface that is identical to the one used by the ADSP-21020
EZ-ICE Emulator. Commands are accessed from pull-down
menus with a mouse.
PROM Splitter
Formats an executable file into files that can be used with an
industry-standard PROM programmer.
C Compiler and Runtime Library
The C Compiler complies with ANSI specifications. It takes
advantage of the ADSP-21020’s high-level language architec-
tural features and incorporates optimizing algorithms to speed
up the execution of code. It includes an extensive runtime
library with over 100 standard and DSP-specific functions.
C Source Level Debugger
A full-featured C source level debugger that works with the
simulator or EZ-ICE emulator to allow debugging of
assembler source, C source, or mixed assembler and C.
Numerical C Compiler
Supports ANSI Standard (X3J11.1) Numerical C as defined
by the Numeric C Extensions Group. The compiler accepts C
source input containing Numerical C extensions for array
selection, vector math operations, complex data types,
circular pointers, and variably dimensioned arrays, and
outputs ADSP-21xxx assembly language source code.
ADSP-21020 EZ-LAB® Evaluation Board
The EZ-LAB Evaluation Board is a general-purpose, stand-
alone ADSP-21020 system that includes 32K words of
program memory and 32K words of data memory as well as
analog I/O. A PC RS-232 download path enables the user to
download and run programs directly on the EZ-LAB. In
addition, it may be used in conjunction with the EZ-ICE
Emulator to provide a powerful software debug environment.
ADSP-21020 EZ-ICE® Emulator
This in-circuit emulator provides the system designer with a
PC-based development environment that allows nonintrusive
access to the ADSP-21020’s internal registers through the
processor’s 5-pin JTAG Test Access Port. This use of on-chip
emulation circuitry enables reliable, full-speed performance in
any target. The emulator uses the same graphical user inter-
face as the ADSP-21020 Simulator, allowing an easy tran-
sition from software to hardware debug. (See “Target System
Requirements for Use of EZ-ICE Emulator” on page 27.)
This data sheet provides a general overview of ADSP-21020
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-21020 User’s
Manual. For development system and programming reference
information, refer to the ADSP-21000 Family Development
Software Manuals and the ADSP-21020 Programmer’s Quick
Reference. Applications code listings and benchmarks for key
DSP algorithms are available on the DSP Applications BBS; call
(617) 461-4258, 8 data bits, no parity, 1 stop bit, 300/1200/
2400/9600 baud.
Figure 1 shows a block diagram of the ADSP-21020. The
processor features:
Three Computation Units (ALU, Multiplier, and Shifter)
with a Shared Data Register File
Two Data Address Generators (DAG 1, DAG 2)
Program Sequencer with Instruction Cache
32-Bit Timer
Memory Buses and Interface
JTAG Test Access Port and On-Chip Emulation Support
Computation Units
The ADSP-21020 contains three independent computation
units: an ALU, a multiplier with fixed-point accumulator, and a
shifter. In order to meet a wide variety of processing needs, the
computation units process data in three formats: 32-bit
fixed-point, 32-bit floating-point and 40-bit floating-point. The
floating-point operations are single-precision IEEE-compatible
(IEEE Standard 754/854). The 32-bit floating-point format is
EZ-LAB and EZ-ICE are registered trademarks of Analog Devices, Inc.
–2– REV. C

Features a FEATURES Supersca lar IEEE Floating-Point Processor Off-C hip Harvard Architecture Maximizes Sign al Processing Performance 30 ns, 33.3 M IPS Instruction Rate, Single-Cycle Exec ution 100 MFLOPS Peak, 66 MFLOPS Sustai ned Performance 1024-Point Complex FFT Benchmark: 0.58 ms Divide (y/x): 180 ns Inverse Square Root (1/√x ): 270 ns 32-Bit Single-Precision and 40-Bit Exte nded-Precision IEEE Floating-Point Data Formats 32-Bit Fixed-Point Formats, In teger and Fractional, with 80-Bit Accum ulators IEEE Exception Handling with In terrupt on Exception Three Independent Computation Units: Multiplier, ALU, and Barrel Shifter Dual Data Address Gener ators with Indirect, Immediate, Modulo, and Bit Reverse Addressing Modes Two O ff-Chip Memory Transfers in Parallel wi th Instruction Fetch and Single-Cycle M ultiply & ALU Operations Multiply with Add & Subtract for FFT Butterfly Comput ation Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup Single-Cycle Regi.
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