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DP83257 Dataheets PDF



Part Number DP83257
Manufacturers National Semiconductor
Logo National Semiconductor
Description (DP83256 / DP83257) PLAYER Device
Datasheet DP83257 DatasheetDP83257 Datasheet (PDF)

www.DataSheet4U.com DP83256 56-AP 57 PLAYER a Device (FDDI Physical Layer Controller) PRELIMINARY October 1994 DP83256 56-AP 57 PLAYER a TM Device (FDDI Physical Layer Controller) General Description The DP83256 56-AP 57 Enhanced Physical Layer Controller (PLAYER a device) implements one complete Physical Layer (PHY) entity as defined by the Fiber Distributed Data Interface (FDDI) ANSI X3T9 5 standard The PLAYER a device integrates state of the art digital clock recovery and improved clock ge.

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www.DataSheet4U.com DP83256 56-AP 57 PLAYER a Device (FDDI Physical Layer Controller) PRELIMINARY October 1994 DP83256 56-AP 57 PLAYER a TM Device (FDDI Physical Layer Controller) General Description The DP83256 56-AP 57 Enhanced Physical Layer Controller (PLAYER a device) implements one complete Physical Layer (PHY) entity as defined by the Fiber Distributed Data Interface (FDDI) ANSI X3T9 5 standard The PLAYER a device integrates state of the art digital clock recovery and improved clock generation functions to enhance performance eliminate external components and remove critical layout requirements FDDI Station Management (SMT) is aided by Link Error Monitoring support Noise Event Timer (TNE) support Optional Auto Scrubbing support an integrated configuration switch and built-in functionality designed to remove all stringent response time requirements such as PC React and CF React Y Y Y Y Y Y Y Y Y Y Y Features Y Y Y Y Y Y Single chip FDDI Physical Layer (PHY) solution Integrated Digital Clock Recovery Module provides enhanced tracking and greater lock acquisition range Integrated Clock Generation Module provides all necessary clock signals for an FDDI system from an external 12 5 MHz reference Y Y Y Alternate PMD Interface (DP83256-AP 57) supports UTP twisted pair FDDI PMDs with no external clock recovery or clock generation functions required No External Filter Components Connection Management (CMT) Support (LEM TNE PC React CF React Auto Scrubbing) Full on-chip configuration switch Low Power CMOS-BIPOLAR design using a single 5V supply Full duplex operation with through parity Separate management interface (Control Bus) Selectable Parity on PHY-MAC Interface and Control Bus Interface Two levels of on-chip loopback 4B 5B encoder decoder Framing logic Elasticity Buffer Repeat Filter and Smoother Line state detector generator Supports single attach stations dual attach stations and concentrators with no external logic DP83256 for SAS DAS single path stations DP83257 for SAS DAS single dual path stations DP83256-AP for SAS DAS single path stations that require the alternate PMD interface TL F 11708 – 1 FIGURE 1-1 FDDI Chip Set Overview TRI-STATE is a registered trademark of National Semiconductor Corporation BMACTM BSITM CDDTM CDLTM CRDTM CYCLONETM MACSITM PLAYERTM PLAYER a TM and TWISTERTM are trademarks of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 11708 RRD-B30M115 Printed in U S A Table of Contents 1 0 FDDI CHIP SET OVERVIEW 1 1 FDDI 2-Chip Set 1 2 FDDI TP-PMD Solutions 2 0 ARCHITECTURE DESCRIPTION 2 1 Block Overview 2 2 Interfaces 3 0 FUNCTIONAL DESCRIPTION 3 1 Clock Recovery Module 3 2 Receiver Block 3 3 Transmitter Block 3 4 Configuration Switch 3 5 Clock Generation Module 3 6 Station Management Support 3 7 PHY-MAC Interface 3 8 PMD Interface 4 0 MODES OF OPERATION 4 1 Run Mode 4 2 Stop Mode 4 3 Loopback Mode 4 4 Device Reset 4 5 Cascade Mode 5 0 REGISTERS 5 1 Mode Register (MR) 5 2 Configuration Register (CR) 5 3 Interrupt Condition Register (ICR) 5 4 Interrupt Condition Mask Register (ICMR) 5 5 Current Transmit State Register (CTSR) 5 6 Injection Threshold Register (IJTR) 5 7 Injection Symbol Register A (ISRA) 5 8 Injection Symbol Register B (ISRB) 5 9 Current Receive State Register (CRSR) 5 10 Receive Condition Register A (RCRA) 5 11 Receive Condition Register B (RCRB) 5 12 Receive Condition Mask Register A (RCMRA) 5 13 Receive Condition Mask Register B (RCMRB) 5 14 Noise Threshold Register (NTR) 5 15 Noise Prescale Threshold Register (NPTR) 5 16 Current Noise Count Register (CNCR) 5 17 Current Noise Prescale Count Register (CNPCR) 5 18 State Threshold Register (STR) 5 19 State Prescale Threshold Register (SPTR) 5 20 Current State Count Register (CSCR) 5 21 Current State Prescale Count Register (CSPCR) 5 22 Link Error Threshold Register (LETR) 5 23 Current Link Error Count Register (CLECR) 5 24 User Definable Register (UDR) 5 25 Device ID Register (DIR) 5 26 Current Injection Count Register (CIJCR) 5 27 Interrupt Condition Comparison Register (ICCR) 5 28 Current Transmit State Comparison Register (CTSCR) 5 29 Receive Condition Comparison Register A (RCCRA) 5 30 Receive Condition Comparision Register B (RCCRB) 5 31 Mode Register 2 (MODE2) 5 32 CMT Condition Comparison Register (CMTCCR) 5 33 CMT Condition Register (CMTCR) 5 34 CMT Condition Mask Register (CMTCMR) 5 35 Reserved Registers 22H-23H (RR22H-RR23H) 5 36 Scrub Timer Threshold Register (STTR) 5 37 Scrub Timer Value Register (STVR) 5 38 Trigger Definition Register (TDR) 5 39 Trigger Transition Configuration Register (TTCR) 5 40 Reserved Registers 28H-3AH (RR28H-RR3AH) 5 41 Clock Generation Module Register (CGMREG) 5 42 Alternate PMD Register (APMDREG) 5 43 Gain Register (GAINREG) 5 44 Reserved Registers 3EH-3FH (RR3EH-RR3FH) 6 0 SIGNAL DESCRIPTIONS 6 1 DP83256VF Signal Descriptions 6 2 DP83256VF-AP Signal Descriptions 6 3 DP83257VF Signal Descriptions 7 0 ELECTRICAL CHARACTERISTICS 7.


DP83256 DP83257 DP83261


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