HDMP-1637A

www.DataSheet4U.com Gigabit Ethernet SerDes Circuit with Differential PECL Clock Inputs HDMP-1637A SerDes Features IEEE 802.3z Gigabit Ethernet Compatible, Supports 1250 MBd Gigabit Ethernet Based on X3T11 “10 Bit Specification” Low Power Consumption 10 mm 64-pin PQFP Package Transmitter and Receiver Functions Incorporated onto a Single IC 5-Volt Tolerant I/Os 10 Bit Wide Parallel TTL Compatible I/Os Single +3.3 V Power Supply Differential PECL Clock Inputs 2 kV Human Body ESD Protection on all Pins transmission, incorporating both the Gigabit Ethernet transmit and receive functions into a single device. This chip is used to build a high speed interface (as shown in Figure 1) while minimizing board space, power, and cost. It is compatible with the IEEE 802.3z specification. The transmitter section accepts 10-bit wide parallel TTL data and serializes this data into a high speed serial data stream. The parallel data is expected to be “8B/10B” encoded data, or equivalent. This parallel data is latched into the input register of the transmitter section on the rising edge of the 125 MHz reference clock (used as the transmit byte clock). The transmitter section’s PLL locks to this user supplied 125 MHz byte clock. This clock is then multiplied by 10, to generate the 1250 MHz serial signal clock used to generate the high speed output. The high speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber op...