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DP83223
April, 1997
DP83223 TWISTER High Speed Networking Transceiver Device
General Description
The DP83223 Twisted Pair Transceiver is an integrated circuit capable of driving and receiving three-level (MLT-3) encoded datastreams. The DP83223 Transceiver is designed to interface directly with National Semiconductor’s Fast Ethernet and FDDI Chip Sets or similar Physical Layer silicon allowing low cost data links over copper based media. The DP83223 allows links of up to 100 meters over Shielded Twisted Pair (Type-1A STP) and Category-5 datagrade Unshielded Twisted Pair (Cat-5 UTP) or equivalent. The DP83223 is available in a 28 pin PLCC package and a 32 pin PQFP package.
Features
s s s s s s s s s Compatible with ANSI X3.263 TP-PMD draft standard Allows use of Type 1 STP and Category 5 UTP cables Requires a single +5V supply Integrated transmitter and receiver with adaptive equalization circuit Isolated TX and RX power supplies for minimum noise coupling Loopback feature for board diagnostics Digitally Synthesized transmit signal transition time control for reduced EMI Programmable transmit voltage amplitude Suitable for 100BASE-TX Fast Ethernet and Twisted Pair FDDI applications
System Connection Diagrams DP83257VF or DP83256VF-AP PLAYER+
TX DATA Descrambled RX DATA Recovered RXDATA
DP83840A 10/100 Ethernet PHY
TXC
Phased RX CLOCK
Recovered RXCLOCK RX DATA
DP83222 Stream Cipher
Scrambled TX DATA Scrambled RX DATA Signal Detect SIGDET Scrambled TX DATA
DP83223 Transceiver
PMD Encoded TXDATA PMD Encoded RXDATA
DP83223 Transceiver
PMD Encoded TXDATA PMD Encoded RXDATA
Magnetics
Magnetics
Twisted Pair Media
Twisted Pair Media
100BASE-TX
© 1997 National Semiconductor Corporation
Twisted Pair FDDI
1
DP83223
General Description (Continued) Table of Contents
1.0 2.0 3.0 Connection Diagram Pin Description Functional Description 3.1 Overview 3.2 MLT-3 Encoding 3.3 Transition Time Control 3.4 Adaptive Equalization 3.5 Jitter Performance DC and AC Specifications 4.1 TRANSMIT TIMING 4.2 RECEIVE PROPAGATION DELAY 4.3 LOOPBACK PROPAGATION DELAY 4.4 SIGNAL DETECT TIMING 4.5 ADAPTIVE EQUALIZER TIMING
4.0
Block Diagram
TXREF PMRD+ PMRD-
Programmable Current Output Driver
TXO+
TXOLB
EQSEL RXI + RXI CDET
SD DATA
PMID + MUX LOGIC Equalizer Amp/ Signal Detect
Comparators/ Control Logic
PMID -
SD+
LBEN
SD-
Revision A
2
DP83223
1.0 Connection Diagram
RXGND RXGND
RXVCC
RXVCC
27
RXI+
RXI-
TXVCC TXREF TXGND TXOTXO+ TXGND TXVCC
4 5 6 7 8 9 10 11 12
3
2
1
28
VCC
26 25 24 23
PMID+ PMIDEXTVCC GND SDSD+ LBEN
DP83223V
13 14 15 16 17 18
22 21 20 19
ENCSEL
VCC
EQSEL
PMRD+
28 Pin PLCC Order Number DP83223V See NS Package Number V28A RXGND RXGND RXVCC RXVCC
26
RXI+
RXI-
PMRD-
CDET VCC
25
N/C
32
31
30
29
GND
28
27
TXVCC TXREF TXGND TXOTXO+ TXGND TXVCC N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22
N/C PMID+ PMIDEXTVCC GND SDSD+ LBEN
DP83223VBE
21 20 19 18 17
ENCSEL
VCC
PMRD+
PMRD-
EQSEL
GND
32 Pin PQFP Order Number DP83223VBE See NS Package Number VBE32A
3
CDET
N/C
DP83223
2.0 Pin Description
DP83223 Pinout Summary
Symbol Pin No PLCC(PQFP) VCC GND RXVcc 13,26 (10, 25) 14, 22(11 ,20) 4, 27(26, 31) Supply Supply Supply Vcc: Positive power supply for the ECL compatible circuitry. The Transceiver operates from a single +5VDC power supply. GND: Return path for the ECL compatible circuitry power supply. Receive Vcc: Positive power supply for the small signal receive circuitry. This power supply is intentionally separated from others to eliminate receive errors due to coupled supply noise. Receive GND: Return path for the receive power supply circuitry. This power supply return is intentionally separated from others to eliminate receive errors due to coupled supply noise. Transmit Vcc: Positive power supply required by the analog portion of the transmit circuitry. This power supply is intentionally separated from the others to prevent supply noise from coupling to the transmit outputs. Transmit GND: Return path for the analog transmit power supply circuitry. This supply return is intentionally separated from others to prevent supply noise from being coupled to the transmit outputs. External Vcc: Positive power supply for ECL output circuitry. Type Description
RXGND
3, 28(27, 30)
Supply
TXVcc
5, 11(1, 7)
Supply
TXGND
7, 10(3, 6)
Supply
EXTVcc RXI+/PMID+/-
23(21) 2, 1(29, 28) 25, 24(23, 22)
Supply
Differential Receive Data Inputs: Balanced differential line receiver inputs. Voltage In ECL Out Physical Media Indicate Data: Differential ECL compatible outputs source the recovered receive data back to the Physical Layer device or to a separate clock recovery device. Physical Media Request Data: Differential ECL compatible inputs which receive data from Physical Layer Device.
PMRD+/TXO+/-
15, 16(12,13) 9, 8(5,4)
ECL In
Differential Transmit Data Outputs: Differential current driver outputs which drive Current MLT-3 encoded data .