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UPD44321181 Dataheets PDF



Part Number UPD44321181
Manufacturers NEC
Logo NEC
Description (UPD44321181 / UPD44321361) 32M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
Datasheet UPD44321181 DatasheetUPD44321181 Datasheet (PDF)

www.DataSheet4U.com DATA SHEET MOS INTEGRATED CIRCUIT µ PD44321181, 44321361 32M-BIT ZEROSBTM SRAM FLOW THROUGH OPERATION Description The µPD44321181 is a 2,097,152-word by 18-bit and the µPD44321361 is a 1,048,576-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44321181 and µPD44321361 are optimized to eliminate dead cycles for read to write, or write to read transitions. These ZEROSB static RAMs integrate unique sy.

  UPD44321181   UPD44321181


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www.DataSheet4U.com DATA SHEET MOS INTEGRATED CIRCUIT µ PD44321181, 44321361 32M-BIT ZEROSBTM SRAM FLOW THROUGH OPERATION Description The µPD44321181 is a 2,097,152-word by 18-bit and the µPD44321361 is a 1,048,576-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44321181 and µPD44321361 are optimized to eliminate dead cycles for read to write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The µPD44321181 and µPD44321361 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The µPD44321181 and µPD44321361 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and low capacitive loading. Features • Low voltage core supply: VDD = 3.3 ± 0.165 V / 2.5 ± 0.125 V • Synchronous operation • 100 percent bus utilization • Internally self-timed write control • Burst read / write : Interleaved burst and linear burst sequence • Fully registered inputs and outputs for flow through operation • All registers triggered off positive clock edge • 3.3V or 2.5V LVTTL Compatible : All inputs and outputs • Fast clock access time : 7.5 ns (117 MHz) • Asynchronous output enable : /G • Burst sequence selectable : MODE • Sleep mode : ZZ (ZZ = Open or Low : Normal operation) • Separate byte write enable : /BW1 to /BW4 (µPD44321361) /BW1 and /BW2 (µPD44321181) • Three chip enables for easy depth expansion • Common I/O using three state outputs The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information. Document No. M15958EJ5V0DS00 (5th edition) Date Published April 2005 NS CP(K) Printed in Japan The mark shows major revised points. 2002, 2005 µPD44321181, 44321361 Ordering Information Part number Access Time ns Clock Frequency MHz 117 Core Supply Voltage V 3.3 ± 0.165 2.5 ± 0.125 3.3 V or 2.5 V LVTTL 100-pin PLASTIC LQFP 2.5 V LVTTL 3.3 V or 2.5 V LVTTL 2.5 V LVTTL (14 x 20) I/O Interface Package µPD44321181GF-A75 7.5 µPD44321361GF-A75 7.5 117 3.3 ± 0.165 2.5 ± 0.125 2 Data Sheet M15958EJ5V0DS µPD44321181, 44321361 Pin Configurations /××× indicates active low signal. 100-pin PLASTIC LQFP (14 × 20) [µPD44321181GF] Marking Side /BW2 /BW1 /CKE /CE2 ADV CLK CE2 /WE A18 A17 VDD VSS /CE NC NC A6 A7 A8 A9 /G 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC NC VDDQ VSSQ NC NC I/O9 I/O10 VSSQ VDDQ I/O11 I/O12 VSS VDD VDD VSS I/O13 I/O14 VDDQ VSSQ I/O15 I/O16 I/OP2 NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A20 NC NC VDDQ VSSQ NC I/OP1 I/O8 I/O7 VSSQ VDDQ I/O6 I/O5 VSS VSS VDD ZZ I/O4 I/O3 VDDQ VSSQ I/O2 I/O1 NC NC VSSQ VDDQ NC NC NC MODE VSS VDD A19 A10 A11 A12 A13 A14 A15 Remark Refer to Package Drawing for the 1-pin index mark. A16 NC NC NC A5 A4 A3 A2 A1 A0 Data Sheet M15958EJ5V0DS 3 µPD44321181, 44321361 Pin Identifications [µPD44321181GF] Symbol A0 to A20 Pin No. 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 83, 84, 43, 80 I/O1 to I/O16 58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In, 18, 19, 22, 23 I/OP1, I/OP2 74, 24 Synchronous / Asynchronous Data Out Synchronous Data In (Parity), Synchronous / Asynchronous Data Out (Parity) ADV /CE, CE2, /CE2 /WE /BW1, /BW2 /G CLK /CKE MODE 85 98, 97, 92 88 93, 94 86 89 87 31 Synchronous Address Load / Advance Input Synchronous Chip Enable Input Synchronous Write Enable Input Synchronous Byte Write Enable Input Asynchronous Output Enable Input Clock Input Synchronous Clock Enable Input Asynchronous Burst Sequence Select Input Have to tied to VDD or VSS during normal operation ZZ VDD VSS VDDQ VSSQ NC 64 15, 16, 41, 65, 91 14, 17, 40, 66, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 51, 52, 53, 56, 57, 75, 78, 79, 95, 96 Asynchronous Power Down State Input Power Supply Ground Output Buffer Power Supply Output Buffer Ground No Connection Description Synchronous Address Input 4 Data Sheet M15958EJ5V0DS µPD44321181, 44321361 100-pin PLASTIC LQFP (14 × 20) [.


SY88983V UPD44321181 UPD44321361


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