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UPD44324095 Dataheets PDF



Part Number UPD44324095
Manufacturers NEC
Logo NEC
Description (UPD44324xx5) 36M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION
Datasheet UPD44324095 DatasheetUPD44324095 Datasheet (PDF)

www.DataSheet4U.com PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD44324085, 44324095, 44324185, 44324365 36M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION Description The µPD44324085 is a 4,194,304-word by 8-bit, the µPD44324095 is a 4,194,304-word by 9-bit, the µPD44324185 is a 2,097,152-word by 18-bit and the µPD44324365 is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD4.

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www.DataSheet4U.com PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD44324085, 44324095, 44324185, 44324365 36M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION Description The µPD44324085 is a 4,194,304-word by 8-bit, the µPD44324095 is a 4,194,304-word by 9-bit, the µPD44324185 is a 2,097,152-word by 18-bit and the µPD44324365 is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44324085, µPD44324095, µPD44324185 and µPD44324365 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC FBGA. Features • 1.8 ± 0.1 V power supply and HSTL I/O • DLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports • DDR read or write operation initiated each cycle • Pipelined double data rate operation • Separate data input/output bus • Two-tick burst for low DDR transaction size • Two input clocks (K and /K) for precise DDR timing at clock rising edges only • Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving device • Internally self-timed write control • Clock-stop capability with µs restart • User programmable impedance output • Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz) • Simple control logic for easy depth expansion • JTAG boundary scan The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M16782EJ1V0DS00 (1st edition) Date Published October 2004 NS CP(K) Printed in Japan The mark shows major revised points. 2003 µPD44324085, 44324095, 44324185, 44324365 Ordering Information Part number Cycle Time ns Clock Frequency MHz 300 250 200 300 250 200 300 250 200 300 250 200 1M x 36-bit 2 M x 18-bit 4 M x 9-bit 4 M x 8-bit Organization (word x bit) Core Supply Voltage V 1.8 ± 0.1 HSTL 165-pin PLASTIC FBGA (13 x 15) I/O Interface Package µPD44324085F5-E33-EQ2 Note µPD44324085F5-E40-EQ2 µPD44324085F5-E50-EQ2 µPD44324095F5-E33-EQ2 Note µPD44324095F5-E40-EQ2 µPD44324095F5-E50-EQ2 µPD44324185F5-E33-EQ2 µPD44324185F5-E40-EQ2 µPD44324185F5-E50-EQ2 µPD44324365F5-E33-EQ2 µPD44324365F5-E40-EQ2 µPD44324365F5-E50-EQ2 Note Note 3.3 4.0 5.0 3.3 4.0 5.0 3.3 4.0 5.0 3.3 4.0 5.0 Note Under development 2 Preliminary Data Sheet M16782EJ1V0DS µPD44324085, 44324095, 44324185, 44324365 Pin Configurations /××× indicates active low signal. 165-pin PLASTIC FBGA (13 x 15) (Top View) [µPD44324085F5-EQ2] 1 A B C D E F G H J K L M N P R /CQ NC NC NC NC NC NC /DLL NC NC NC NC NC NC TDO 2 VSS NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A 4 R, /W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 /NW1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 /K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C /C 7 NC /NW0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 /LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI A D0 to D7 Q0 to Q7 /LD R, /W /NW0, /NW1 K, /K C, /C CQ, /CQ ZQ /DLL : Address inputs : Data inputs : Data outputs : Synchronous load : Read Write input : Nibble Write data select : Input clock : Output clock : Echo clock : Output impedance matching : DLL disable TMS TDI TCK TDO VREF VDD VDDQ VSS NC : IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : Ground : No connection Remarks 1. Refer to Package Drawing for the index mark. 2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb. Preliminary Data Sheet M16782EJ1V0DS 3 µPD44324085, 44324095, 44324185, 44324365 165-pin PLASTIC FBGA (13 x 15) (Top View) [µPD44324095F5-EQ2] 1 A B C D E F G H J K L M N P R /CQ NC NC NC NC NC NC /DLL NC NC NC NC NC NC TDO 2 VSS NC NC D5 NC NC D6 VREF NC NC Q7 NC D8 NC TCK 3 A NC NC NC Q5 NC Q6 VDDQ NC NC D7 NC NC Q8 A 4 R, /W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NC NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 /K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C /C 7 NC /BW0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 /LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC D3 NC NC .


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