ADP3193 Controller Datasheet

ADP3193 Datasheet PDF, Equivalent


Part Number

ADP3193

Description

8-Bit Programmable Synchronous Buck Controller

Manufacture

Analog Devices

Total Page 30 Pages
Datasheet
Download ADP3193 Datasheet


ADP3193
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8-Bit Programmable 2- to 3-Phase
Synchronous Buck Controller
ADP3193
FEATURES
Selectable 2- or 3-phase operation at up to 1 MHz per phase
±7.7 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to external high
power drivers
Enhanced PWM flex mode for excellent load transient
performance
Active current balancing between all output phases
Built-in power-good/crowbar blanking supports on-the-fly
VID code changes
Digitally programmable 0.5 V to 1.6 V output supports both
VR10.x and VR11 specifications
Programmable short-circuit protection with programmable
latch-off delay
APPLICATIONS
Desktop PC power supplies for
Next generation Intel® processors
VRM modules
GENERAL DESCRIPTION
The ADP31931 is a highly efficient, multiphase, synchronous buck
switching regulator controller optimized for converting a 12 V
main supply into the core supply voltage required by high per-
formance Intel processors. It uses an internal 8-bit DAC to read
a voltage identification (VID) code directly from the processor,
which is used to set the output voltage between 0.5 V and 1.6 V.
This device uses a multimode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase relation-
ship of the output signals can be programmed to provide 2- or
3-phase operation, allowing for the construction of up to three
complementary buck switching stages.
The ADP3193 also includes programmable no load offset and
slope functions to adjust the output voltage as a function of the
load current, optimally positioning it for a system transient. The
ADP3193 also provides accurate and reliable short-circuit
protection, adjustable current limiting, and a delayed power-
good output that accommodates on-the-fly output voltage
changes requested by the CPU.
FUNCTIONAL BLOCK DIAGRAM
GND 14
VCC
23
SHUNT
REGULATOR
UVLO
SHUTDOWN
850mV –
EN 1
+
DAC
+ 150mV
CSREF
+
+
DAC –
– 350mV
PWRGD 2
DELAY
ILIMIT 8
DELAY 7
RT RAMPADJ
9 10
OSCILLATOR
+
CMP
SET EN
RESET
15 OD
22 PWM1
+
CMP
+
CMP
21 PWM2
RESET
2/3-PHASE
DRIVER LOGIC
20 PWM3
RESET
CROWBAR
CURRENT
LIMIT
19 SW1
18 SW2
17 SW3
13 CSCOMP
CURRENT
MEASUREMENT
+
11 CSREF
AND LIMIT
12 CSSUM
IREF 16
COMP 5
4 FB
FBRTN 3
PRECISION
REFERENCE
VIDSEL 32
VC DAC
24 25 26 27 28 29 30 31
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
BOOT
VOLTAGE
AND
SOFT START
CONTROL
6 SS
ADP3193
Figure 1.
The ADP3193 has a built-in shunt regulator that allows the part
to be connected to the 12 V system supply through a series resistor.
The ADP3193 is specified over the extended commercial
temperature range of 0°C to 85°C and is available in a
32-lead LFCSP.
1 Protected by U.S. Patent Number 6,683,441; other patents pending.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.

ADP3193
www.DataSheet4U.com
ADP3193
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Test Circuits....................................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ........................................................................ 9
Start-Up Sequence........................................................................ 9
Phase Detection Sequence........................................................... 9
Master Clock Frequency............................................................ 10
Output Voltage Differential Sensing ........................................ 10
Output Current Sensing ............................................................ 10
Current Control Mode and Thermal Balance ........................ 10
Voltage Control Mode................................................................ 10
Current Reference ...................................................................... 11
Enhanced PWM Mode .............................................................. 11
Delay Timer................................................................................. 11
Soft Start ...................................................................................... 11
Current-Limit, Short-Circuit, and Latch-Off Protection...... 11
REVISION HISTORY
8/06—Revision A: Initial Version
Dynamic VID ............................................................................. 12
Power-Good Monitoring........................................................... 12
Output Crowbar ......................................................................... 12
Output Enable and UVLO ........................................................ 13
Application Information................................................................ 19
Setting the Clock Frequency..................................................... 19
Soft Start Delay Time................................................................. 19
Current-Limit Latch-Off Delay Times .................................... 19
Inductor Selection ...................................................................... 19
Current Sense Amplifier............................................................ 20
Inductor DCR Temperature Correction ................................. 21
Output Offset .............................................................................. 21
COUT Selection ............................................................................. 21
Power MOSFETs......................................................................... 22
Ramp Resistor Selection............................................................ 24
COMP Pin Ramp ....................................................................... 24
Current-Limit Setpoint.............................................................. 24
Feedback Loop Compensation Design.................................... 24
CIN Selection and Input Current di/dt Reduction.................. 26
Shunt Resistor Design................................................................ 26
Tuning the ADP3193 ................................................................. 27
Layout and Component Placement ......................................... 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
Rev. A | Page 2 of 32


Features www.DataSheet4U.com 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controll er ADP3193 FEATURES Selectable 2- or 3- phase operation at up to 1 MHz per phas e ±7.7 mV worst-case differential sens ing error over temperature Logic-level PWM outputs for interface to external h igh power drivers Enhanced PWM flex mod e for excellent load transient performa nce Active current balancing between al l output phases Built-in power-good/cro wbar blanking supports on-the-fly VID c ode changes Digitally programmable 0.5 V to 1.6 V output supports both VR10.x and VR11 specifications Programmable sh ort-circuit protection with programmabl e latch-off delay FUNCTIONAL BLOCK DIA GRAM VCC 23 RT RAMPADJ 9 10 SHUNT REG ULATOR UVLO SHUTDOWN GND 14 850mV EN 1 OSCILLATOR + – 15 OD PWM1 PWM2 PWM 3 CMP – + DAC + 150mV CSREF DAC – 350mV + – – + CURRENT BALANCING CIR CUIT SET EN RESET 22 21 CMP – + RESET 2/3-PHASE DRIVER LOGIC 20 CMP + RESET CURRENT LIMIT 19 18 PWRGD 2 DELAY CROWBAR SW1 SW2 SW3 CSCOMP.
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