WED2EG472512V-D2

www.DataSheet4U.com White Electronic Designs WED2EG472512V-D2 ADVANCED* 16MB (4x512Kx72) SYNC BURST PIPELINE, DUAL KEY DIMM FEATURES 4x512Kx72 Synchronous Burst Pipeline Architecture; Dual Cycle Deselect Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable (EM#) Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#) Clock Controlled Byte Write Mode Enable (BWE#) Clock Controlled Byte Write Enables (BW1#-BW8#) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW#) Asynchronous Output Enable (G#) Internally Self-Timed Write Individual Bank Sleep Mode Enables (ZZ1, ZZ2, ZZ3, ZZ4) Gold Lead Finish 3.3V ± 10% Operation Frequency(s): 200, 166, 150 and 133MHZ Access Apeed(s): tKHQV = 3.0, 3.5, 3.7 and 4.0ns Common Data I/O High Capacitance (30pF) Drive, at Rated Access Speed Single Total Array Clock Multiple VCC and GND for Improved Noise Immunity * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. DESCRIPTION The WED2EG472512V is a Synchronous/Synchronous Burst SRAM, 84 position Dual Key; Double High DIMM (168 contacts) Module, organized as 4x512Kx72. The Module contains sixteen (16) Synchronous Burst RAM devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The Module Architecture is defined as a Sync/SyncBurst, Pipeline, with support for either linear or sequential burst. This Module ...