A43L1632 DRAM Datasheet

A43L1632 Datasheet PDF, Equivalent


Part Number

A43L1632

Description

512K X 32 Bit X 4 Banks Synchronous DRAM

Manufacture

AMIC Technology

Total Page 30 Pages
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A43L1632
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A43L1632
Preliminary
512K X 32 Bit X 4 Banks Synchronous DRAM
Document Title
512K X 32 Bit X 4 Banks Synchronous DRAM
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
December 28, 2004
Remark
Preliminary
PRELIMINARY (December, 2004, Version 0.0)
AMIC Technology, Corp.

A43L1632
A43L1632
Preliminary
512K X 32 Bit X 4 Banks Synchronous DRAM
Features
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks / Pulse RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Deep Power Down Mode
Burst Read Single-bit Write operation
Clock Frequency (max) : 166MHz @ CL=3 (-6)
143MHz @ CL=3 (-7)
General Description
The A43L1632 is 67,108,864 bits Low Power synchronous
high data rate Dynamic RAM organized as 2 X 1,048,576
words by 32 bits, fabricated with AMIC’s high performance
CMOS technology. Synchronous design allows precise
cycle control with the use of system clock. I/O transactions
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
Self refresh with programmable refresh period through
EMRS cycle
Programmable Power Reduction Feature by partial array
activation during Self-refresh through EMRS cycle
86 Pin TSOP (II)
operating temperature range: 0ºC to + 70ºC
are possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
PRELIMINARY (December, 2004, Version 0.0)
1
AMIC Technology, Corp.


Features www.DataSheet4U.com A43L1632 Preliminar y Document Title 512K X 32 Bit X 4 Bank s Synchronous DRAM Revision History Rev . No. 0.0 512K X 32 Bit X 4 Banks Sync hronous DRAM History Initial issue Is sue Date December 28, 2004 Remark Prel iminary PRELIMINARY (December, 2004, Version 0.0) AMIC Technology, Corp. A 43L1632 Preliminary Features JEDEC stan dard 3.3V power supply LVTTL compatible with multiplexed address Four banks / Pulse RAS MRS cycle with address key pr ograms - CAS Latency (2,3) - Burst Leng th (1,2,4,8 & full page) - Burst Type ( Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Deep Power Down Mode B urst Read Single-bit Write operation Cl ock Frequency (max) : 166MHz @ CL=3 (-6 ) 143MHz @ CL=3 (-7) 512K X 32 Bit X 4 Banks Synchronous DRAM DQM for maskin g Auto & self refresh 64ms refresh peri od (4K cycle) Self refresh with program mable refresh period through EMRS cycle Programmable Power Reduction Feature by partial array activati.
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