A43L2616 DRAM Datasheet

A43L2616 Datasheet PDF, Equivalent


Part Number

A43L2616

Description

1M X 16 Bit X 4 Banks Synchronous DRAM

Manufacture

AMIC Technology

Total Page 30 Pages
PDF Download
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A43L2616
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A43L2616
1M X 16 Bit X 4 Banks Synchronous DRAM
Document Title
1M X 16 Bit X 4 Banks Synchronous DRAM
Revision History
Rev. No.
0.0
1.0
2.0
3.0
3.1
History
Initial issue
Add -V grade
Add -5.5 spec
Add Full Page Mode
Add Pb-Free package type
Issue Date
August 9, 2001
November 26,2001
January 4,2002
February 21,2002
September 2, 2004
Remark
(September, 2004, Version 3.1)
AMIC Technology, Corp.

A43L2616
A43L2616
1M X 16 Bit X 4 Banks Synchronous DRAM
Features
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks / Pulse RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Clock Frequency: 166MHz @ CL=3
143MHz @ CL=3
183Mhz @ CL=3
(183Mhz is available only for –V grade)
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
54 Pin TSOP (II)
Low Self Refresh Current version for –V grade
General Description
The A43L2616 is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 X 1,048,576 words by
16 bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock. I/O transactions are
Pin Configuration
TSOP (II)
possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
A43L2616V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
(September, 2004, Version 3.1)
1 AMIC Technology, Corp.


Features www.DataSheet4U.com A43L2616 1M X 16 Bi t X 4 Banks Synchronous DRAM Document T itle 1M X 16 Bit X 4 Banks Synchronous DRAM Revision History Rev. No. 0.0 1.0 2.0 3.0 3.1 History Initial issue Add -V grade Add -5.5 spec Add Full Page Mo de Add Pb-Free package type Issue Date August 9, 2001 November 26,2001 Januar y 4,2002 February 21,2002 September 2, 2004 Remark (September, 2004, Version 3.1) AMIC Technology, Corp. A43L2616 1M X 16 Bit X 4 Banks Synchronous DRAM Features JEDEC standard 3.3V power sup ply LVTTL compatible with multiplexed a ddress Four banks / Pulse RAS MRS cycle with address key programs - CAS Latenc y (2,3) - Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interl eave) All inputs are sampled at the pos itive going edge of the system clock C lock Frequency: 166MHz @ CL=3 143MHz @ CL=3 183Mhz @ CL=3 (183Mhz is available only for –V grade) Burst Read Single -bit Write operation DQM for masking Au to & self refresh 64ms refresh period (4K cycle) 54 Pin TSOP (II).
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