A43L2616A DRAM Datasheet

A43L2616A Datasheet PDF, Equivalent


Part Number

A43L2616A

Description

1M X 16 Bit X 4 Banks Synchronous DRAM

Manufacture

AMIC Technology

Total Page 30 Pages
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A43L2616A
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A43L2616A
Preliminary
1M X 16 Bit X 4 Banks Synchronous DRAM
Document Title
1M X 16 Bit X 4 Banks Synchronous DRAM
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
Remark
November 30, 2004 Preliminary
PRELIMINARY (November, 2004, Version 0.0)
AMIC Technology, Corp.

A43L2616A
A43L2616A
Preliminary
1M X 16 Bit X 4 Banks Synchronous DRAM
Feature
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks / Pulse RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Clock Frequency: 166MHz @ CL=3
143MHz @ CL=3
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
Commercial Temperature Operation : 0°C~70°C
Industrial Temperature Operation : -40°C~85°C for –U
grade
54 Pin TSOP (II) and 54 Balls CSP (8mm x 8mm)
General Description
The A43L2616A is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 X 1,048,576 words by
16 bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock.
Pin Configuration
TSOP (II)
I/O transactions are possible on every clock cycle. Range
of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high
bandwidth, high performance memory system
applications.
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
A43L2616AV
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
PRELIMINARY (November, 2004, Version 0.0)
1
AMIC Technology, Corp.


Features www.DataSheet4U.com A43L2616A Prelimina ry Document Title 1M X 16 Bit X 4 Banks Synchronous DRAM Revision History Rev. No. 0.0 1M X 16 Bit X 4 Banks Synchro nous DRAM History Initial issue Issue Date November 30, 2004 Remark Prelimi nary PRELIMINARY (November, 2004, Ver sion 0.0) AMIC Technology, Corp. A43L 2616A Preliminary Feature JEDEC standar d 3.3V power supply LVTTL compatible wi th multiplexed address Four banks / Pul se RAS MRS cycle with address key progr ams - CAS Latency (2,3) - Burst Length (1,2,4,8 & full page) - Burst Type (Seq uential & Interleave) All inputs are sa mpled at the positive going edge of the system clock Clock Frequency: 166MHz @ CL=3 143MHz @ CL=3 1M X 16 Bit X 4 Ba nks Synchronous DRAM Burst Read Single -bit Write operation DQM for masking Au to & self refresh 64ms refresh period ( 4K cycle) Commercial Temperature Operat ion : 0°C~70°C Industrial Temperature Operation : -40 ° C~85 ° C for –U grade 54 Pin TSOP (II) and 54 Balls CSP (8mm x 8mm) General Descript.
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