A67P8318

www.DataSheet4U.com A67P8318/A67P7336 Preliminary Document Title 256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM History Initial issue Issue Date July 13, 2005 Remark Preliminary PRELIMINARY (July, 2005, Version 0.0) AMIC Technology, Corp. A67P8318/A67P7336 Preliminary Features Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.5V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined applications Three separate chip enables allow wide range of options for CE control, address pipelining Internally self-timed write cycle Selectable BURST mode (Linear or Interleaved) SLEEP mode (ZZ pin) provided Available in 100 pin LQFP package 256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67P8318, A67P7336 SRAMs integrate a 256K X 18, 128K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered singl...