Secure Microcontroller
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Features
General
• High-performance, Low-power secureAVR Core Enhanced RISC Architecture • • • • •...
Description
www.DataSheet4U.com
Features
General
High-performance, Low-power secureAVR Core Enhanced RISC Architecture
– 135 Powerful Instructions (Most Executed in a Single Clock Cycle) Bond Pad Locations Conforming to ISO 7816-2 ESD Protection to ± 6000V Operating Ranges: from 2.7V to 5.5V Compliant with ICAO specifications; EMV 2000 Specifications; PC Industry Compatible Power-saving Wait and Very Low-power Stop Modes Power-up Detection Available in Wafers, Modules, Dual Interface Module, Contactless Module or Inlay and Industry-standard Packages
Contactless Mode
Contactless Interface Controller (CIC) with Full Support for ISO/IEC 14443 Type A and
B Protocols Supply Voltage Clamp and Regulation Full-bridge Power Rectification On-chip Tuning Capacitance: 10 pF up to 120 pF 3.4 MHz Internal Bus Maximum Frequency with a Clock Extracted From the External Clock and 20 (AVR®) or 40 MHz (AdvX) if the Clock is Internally Generated 13.56 MHz Clock Extraction 3.4 MHz Internal Bus Frequency Reader-to-card: – ISO/IEC Type A: 100% ASK Modulation and Modified Miller Bit Coding – ISO/IEC Type B: 10% ASK Modulation and NRZ Bit Coding Card-to-reader: – ISO/IEC Type A: Generation of 847.5Khz Subcarrier with OOK Modulation and Manchester Bit Coding – ISO/IEC Type B: Modulation of Incoming RF Carrier by Resistive Load Switching / Generation of 847.5Khz Subcarrier with BPSK Modulation / NRZ Data Encoding Baud Rates: Up to 424 kbps RF Frame: Up to 256 Bytes
Secure Mic...
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