Secure Microcontroller
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Features
General
• • • • • • • High-performance, Low-power secureAVR™ Enhanced RISC Architecture
– ...
Description
www.DataSheet4U.com
Features
General
High-performance, Low-power secureAVR™ Enhanced RISC Architecture
– 135 Powerful Instructions (Most Executed in a Single Clock Cycle) Low Power Idle and Power-down Modes Bond Pad Locations Conforming to ISO 7816-2 ESD Protection to ± 4000V Operating Ranges: 1.62 to 5.5V Compliant with GSM, 3GPP and EMV 2000 Specifications; PC Industry Compatible Available in Wafers, Modules, and Industry-standard Packages
Memory
288K Bytes of ROM Program Memory 144K Bytes of EEPROM, Including 128 OTP Bytes and 384-byte Bit-addressable Area
– 1 to 128-byte Program / Erase – 1 ms Program / 1 ms Erase – Typically More than 500,000 Write/Erase Cycles at a Temperature of 25oC – 10 Years Data Retention EEPROM Erase Only Mode Write EEPROM With or Without Autoerase – Bit-write Mode (Optional) – Full or Partial Page Erase Mode (Optional) – Block Erase Mode (Optional) 6K Bytes of RAM
Secure Microcontroller for Smart Cards AT90SC 288144RT Summary
Peripherals
One ISO 7816 Controller
– Up to 625kbps at 5 MHz – Compliant with T=0 and T=1 Protocols One I/O Port Programmable Internal Oscillator (Up to 20 MHz on ROM) Two 16-bit Timers Random Number Generator (RNG) 2-level, 7-vector Interrupt Controller Hardware DES and Triple DES (DPA Resistant) Checksum Accelerator CRC 16 Engine (Compliant with ISO/IEC 3309)
Security
Dedicated Hardware for Protection Against SPA/DPA Attacks Protection Against Physical Attack Env...
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