CY2PD817

www.DataSheet4U.com CY2PD817 320-MHz 1:7 PECL to PECL/CMOS Buffer Features DC to 320-MHz operation 50-ps output-output skew 30-ps cycle-cycle jitter 2.5V power supply LVPECL input @ 320-MHz Operation One LVPECL output @ 320-MHz Operation Four LVCMOS/LVTTL outputs @ 250 MHz/160 MHz Two LVCMOS/LVTTL outputs @ 250 MHz/80 MHz 45% to 55% output duty cycle Output divider control Output enable/disable control Operating temperature range: 0°C to +85°C 24-pin TSSOP Description The CY2PD817 is a low-voltage LVPECL-to-LVPECL and LVCMOS fanout buffer designed for servers, data communications, and clock management. The CY2PD817 is ideal for applications requiring mixed differential and single-ended clock distribution. This device accepts an LVPECL input reference clock and provides one LVPECL and six LVCMOS/LVTTL output clocks. The outputs are partitioned into three banks of one, two, and four outputs. The LVPECL output is a buffered copy of the input clock while the LVCMOS outputs are divided by 1, 2, and 4. When CLRDIV is set HIGH, the output dividers are set to 1. In this mode, the maximum input frequency is limited to 250 MHz. When OE is set HIGH, the outputs are disabled in a High-Z state. Block Diagram Pin Configuration VDD PCLKI PCLKI VSS VDD PCLKO PCLKO ÷ 2, ÷ 1 PCLKO PCLKO PCLKI PCLKI ÷ 4, ÷ 1 QA[0:1] QB[0:3] VSS OE CLRDIV OE VDD VSS CLRDIV 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD QA0 QA1 VSS VDD QB0 QB1 VSS VDD QB2...