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EDI9LC644V Dataheets PDF



Part Number EDI9LC644V
Manufacturers WEDC
Logo WEDC
Description 128Kx32 SSRAM/1Mx32 SDRAM
Datasheet EDI9LC644V DatasheetEDI9LC644V Datasheet (PDF)

www.DataSheet4U.com EDI9LC644V 128Kx32 SSRAM/1Mx32 SDRAM EXTERNAL MEMORY SOLUTION FOR TEXAS INSTRUMENTS TMS320C6000 DSP FEATURES DESCRIPTION n Clock speeds: • SSRAM: 200, 166,150, and 133 MHz • SDRAMs: 125 and 100 MHz n n n n n n n DSP Memory Solution • Texas Instruments TMS320C6201 • Texas Instruments TMS320C6701 Packaging: • 153 pin BGA, JEDEC MO-163 3.3V Operating supply voltage Direct control interface to both the SSRAM and SDRAM ports on the “C6x” Common address and databus 65% space sa.

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www.DataSheet4U.com EDI9LC644V 128Kx32 SSRAM/1Mx32 SDRAM EXTERNAL MEMORY SOLUTION FOR TEXAS INSTRUMENTS TMS320C6000 DSP FEATURES DESCRIPTION n Clock speeds: • SSRAM: 200, 166,150, and 133 MHz • SDRAMs: 125 and 100 MHz n n n n n n n DSP Memory Solution • Texas Instruments TMS320C6201 • Texas Instruments TMS320C6701 Packaging: • 153 pin BGA, JEDEC MO-163 3.3V Operating supply voltage Direct control interface to both the SSRAM and SDRAM ports on the “C6x” Common address and databus 65% space savings vs. monolithic solution Reduced system inductance and capacitance The EDI9LC644VxxBC is a 3.3V, 128K x 32 Synchronous Pipeline SRAM and a 1Mx32 Synchronous DRAM array constructed with one 128K x 32 SBSRAM and two 1Mx16 SDRAM die mounted on a multilayer laminate substrate. The device is packaged in a 153 lead, 14mm by 22mm, BGA. The EDI9LC644VxxBC provides a total memory solution for the Texas Instr uments TMS320C6201 and the TMS320C6701 DSPs The Synchronous Pipeline SRAM is available with clock speeds of 200, 166,150, and 133 MHz, allowing the user to develop a fast external memory for the SSRAM interface port . The SDRAM is available in clock speeds of 125 and 100 MHz, allowing the user to develop a fast external memory for the SDRAM interface port . FIG. 1 PIN CONFIGURATION BOTTOM VIEW P IN D ESCRIPTION 7 8 9 2 3 4 5 6 1 A B C D E F G H J K L M N P R T U A0-16 A B C D E F G H J K L M N P R T U Address Bus Data Bus SSRAM Clock SSRAM Address Status Control SSRAM Write Enable SSRAM Output Enable SDRAM Clock SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Write Enable SDRAM Address 10/auto precharge SSRAM Byte Write Enables SDRAM SDQM 0 - 3 Chip Enable SSRAM Device Chip Enable SDRAM Device Power Supply pins, 3.3V Data Bus Power Supply pins, 3.3V (2.5V future) Ground No Connect DQ19 DQ18 VCCQ DQ17 DQ16 VCCQ NC NC A6 NC VCCQ DQ12 DQ13 VCCQ DQ14 DQ15 1 DQ23 DQ22 VCCQ DQ21 DQ20 VCCQ NC NC A7 NC VCCQ DQ11 DQ10 VCCQ DQ9 DQ8 2 VCC VCC VCC VCC VCC VCC NC A8 A9 NC VCC VCC VCC VCC VCC 3 VSS VSS VSS VSS VSS VSS VSS VSS VSS SDCE VSS SDCLK VSS VSS VSS VSS VSS VSS NC VSS VSS VSS NC NC NC NC NC VSS VSS VSS NC NC 6 VCC VCC VCC VCC VCC VCC A2 A1 A0 NC NC VCC VCC VCC VCC VCC VCC 7 DQ24 DQ25 VCCQ DQ26 DQ27 VCCQ A4 A3 A11 A13 A15 VCCQ DQ4 DQ5 VCCQ DQ6 DQ7 8 DQ28 DQ29 VCCQ DQ30 DQ31 VCCQ A5 A10 A12 A14 A16 VCCQ DQ0 DQ1 VCCQ DQ2 DQ3 9 DQ0-31 SSCLK SSADC SSWE SSOE SDCLK SDRAS SDCAS SDWE SDA10 BWE0-3 SSCE SDCE VCC VCCQ VSS NC SDWE SDA10 SDRAS SDCAS VSS NC/A17 NC/A18 NC/A19 BWE2 BWE3 BWE0 BWE1 VSS VSS VSS VSS SSCLK VSS VCC SSADC SSWE SSOE SSCE 4 5 January 2002 Rev. 4 ECO# 14667 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI9LC644V FIG. 2 BLOCK DIAGRAM White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 2 EDI9LC644V OUTPUT FUNCTIONAL DESCRIPTIONS Symbol Type Signal Polarity Function SSCLK SSADS SSOE SSWE SSCE SDCLK SDCE SDRAS SDCAS SDWE Input Input Input Input Input Input Pulse Pulse Pulse Pulse Pulse Pulse Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock. Active Low Active Low When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation to be executed by the SSRAM. SSCE disable or enable SSRAM device operation. Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Active Low Active Low SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3. When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the operation to be executed by the SDRAM. Address bus for SSRAM and SDRAM A0 and A1 are the burst address inputs for the SSRAM During a Bank Active command cycle, A0-9, SDA10 defines the row address (RA0-10) when sampled at the rising clock edge. A0-16, SDA10 Input Level — During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge operation at the end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and A11 defines the bank to be precharged (low = bank A, high = bank B). If SDA10 is low, autoprecharge is disabled. During a Precharge command cycle, SDA 10 is used in conjunction with A11 to control which bank(s) to precharge. If SDA10 is high, both bank A and Bank B will be precharged regardless of the state of A11. If SDA10 is low, then A11 is used to define which bank to precharge. DQ0-31 BWE0-3 VCC, VSS VCCQ Input Output Input Supply Supply Level Pulse — Data Input/Output are multiplexed on the same pins. BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM. BWE0 is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31. Power and ground for the input buffers and the core logic. Data base power supply pins, 3.3V (.


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