Micrel, Inc.
DUAL CML/PECL/LVPECL-to-LVDS TRANSLATOR
SuperLite™
SuperLSYit5e5™855V SY55855V
FEATURES
s Guaranteed fMAX >750MHz over temperature s 1.5Gbps throughput capability s 3.0V to 5.7V power supply s Guaranteed <700ps propagation delay over
temperature s Guaranteed <50ps within-device skew over
temperature s LVDS compatible outputs s Fully differential I/O architecture s Wide operating temperature range: –40°C to +85°C s Available in a tiny 10-pin MSOP package
SuperLite™
DESCRIPTION
The SY55855V is a fully differential, CML/PECL/ LVPECL-to-LVDS translator. It achieves LVDS signaling up to 1.5Gbps, depending on the distance and the characteristics of the media and noise coupling sources. LVDS is intended to drive 50Ω impedance transmission line media such as PCB traces, backplanes, or cables.
SY55855V inputs can be terminated with a single resistor between the true and the complement pins of a given input.
The SY55855V is a member of Micrel’s new SuperLite™ family of high-speed logic devices. This family features very small packaging, high signal integrity, and operation at many different supply voltages.
FUNCTIONAL BLOCK DIAGRAM
D0 Q0 /D0 /Q0 D1 Q1 /D1 /Q1
APPLICATIONS
s High-speed logic s Data communications systems s Wireless communications systems s Telecom systems
SuperLite is a trademark of Micrel, Inc.
M9999-110705
[email protected] or (408) 955-1690
1
Rev.: D Amendment: /0 Issue Date: November 2005
Micrel, Inc.
SuperLite™ SY55855V
PACKAGE/ORDERING INFORMATION
D0 1 /D0 2 D1 3 /D1 4 GND 5
10 VCC 9 Q0 8 /Q0 7 Q1 6 /Q1
10-Pin MSOP (K10-1)
Ordering Information(1)
Part Number SY55855VKI SY55855VKITR(2) SY55855VKG(3)
Package Type K10-1
K10-1
K10-1
SY55855VKGTR(2, 3) K10-1
Operating Range
Industrial Industrial Industrial
Industrial
Package Marking
Lead Finish
855V
Sn-Pb
855V
Sn-Pb
855V with
NiPdAu
Pb-Free bar line indicator Pb-Free
855V with
NiPdAu
Pb-Free bar line indicator Pb-Free
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel.
3. Pb-Free package recommended for new designs.
PIN DESCRIPTION
Pin Number 1, 2
3, 4
5 6, 7
8, 9
10
Pin Name D0, /D0
D1, /D1
GND /Q1, Q1
/Q0, Q0
VCC
Pin Function
CML/PECL/LVPECL Input (Differential). This is one of the inputs. It is converted to LVDS onto the Q0 and /Q0 outputs.
CML/PECL/LVPECL Input (Differential). This is the other input. It is converted to LVDS onto the Q1 and /Q1 outputs.
Ground.
LVDS Output (Differential). This is the other LVDS output. It buffers the CML input that appears at D1, /D1.
LVDS Output (Differential). This is one LVDS output. It buffers the CML input that appears at D0, /D0.
VCC
TRUTH TABLE
D0 D1 Q0 /Q0 Q1 /Q1 0 00 1 0 1 0 10 1 1 0 1 01 0 0 1 1 11 0 1 0
M9999-110705
[email protected] or (408) 955-1690
2
Micrel, Inc.
SuperLite™ SY55855V
FUNCTIONAL DESCRIPTION
Establishing Static Logic Inputs The true pin of an input pair is internally biased to ground
through a 75kΩ resistor. The complement pin of an input pair is internally biased halfway between VCC and ground by a voltage divider consisting of two 75kΩ resistors. In this way, unconnected inputs appear as logic zeros. To keep an input at static logic zero at VCC > 3.0V, leave both inputs
unconnected. For VCC ≤ 3.0V, connect the complement input to VCC and leave the true input unconnected. To make an input static logic one, connect the true input to VCC, leave the complement input unconnected. These are the only two safe ways to cause inputs to be at a static value. In particular, no input pin should be directly connected to ground. All NC (no connect) pins should be unconnected.
VCC X NC /X
NC X NC /X
Figure 1. Hard Wiring a Logic “1” (1)
Note 1. X is either D0 or D1 input. /X is either /D0 or /D1 input.
VCC > 3.0V
NC X VCC /X
VCC ≤ 3.0V Figure 2. Hard Wiring a Logic “0” (1) Note 1. X is either D0 or D1 input. /X is either /D0 or /D1 input.
M9999-110705
[email protected] or (408) 955-1690
3
Micrel, Inc.
LVDS OUTPUTS
LVDS stands for Low Voltage Differential Swing. LVDS specifies a small swing of 350mV typical, on a nominal 1.25V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is also kept tight, to keep EMI low.
50Ω 50Ω
vOD
100Ω ±1%
vOH, vOL
vOH, vOL
SuperLite™ SY55855V
49.9Ω, ±1% 49.9Ω, ±1%
vOCM, ∆vOCM
GND
Figure 4. LVDS Common Mode Measurement
GND Figure 3. LVDS Differential Measurement
50Ω 50Ω
100Ω
Figure 5. LVDS Output Termination
M9999-110705
[email protected] or (408) 955-1690
4
Micrel, Inc.
ABSOLUTE MAXIMUM RATINGS(1)
SuperLite™ SY55855V
Symbol
Rating
Value
Unit
VCC Power Supply Voltage
–0.5 to +6.0
V
VIN IOUT TA TLEAD Tstore
Input Voltage LVDS Output Current Operating Temperature Range Lead Temperature (solderin.